CodegenDriver.cpp revision 100dbe0d8d5b419bc3727e5b8a07e995351fe129 
1/*
2 * Copyright (C) 2009 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17/*
18 * This file contains codegen and support common to all supported
19 * Mips variants.  It is included by:
20 *
21 *        Codegen-$(TARGET_ARCH_VARIANT).c
22 *
23 * which combines this common code with specific support found in the
24 * applicable directory below this one.
25 */
26
27/*
28 * Mark garbage collection card. Skip if the value we're storing is null.
29 */
30static void markCard(CompilationUnit *cUnit, int valReg, int tgtAddrReg)
31{
32    int regCardBase = dvmCompilerAllocTemp(cUnit);
33    int regCardNo = dvmCompilerAllocTemp(cUnit);
34    MipsLIR *branchOver = opCompareBranch(cUnit, kMipsBeq, valReg, r_ZERO);
35    loadWordDisp(cUnit, rSELF, offsetof(Thread, cardTable),
36                 regCardBase);
37    opRegRegImm(cUnit, kOpLsr, regCardNo, tgtAddrReg, GC_CARD_SHIFT);
38    storeBaseIndexed(cUnit, regCardBase, regCardNo, regCardBase, 0,
39                     kUnsignedByte);
40    MipsLIR *target = newLIR0(cUnit, kMipsPseudoTargetLabel);
41    target->defMask = ENCODE_ALL;
42    branchOver->generic.target = (LIR *)target;
43    dvmCompilerFreeTemp(cUnit, regCardBase);
44    dvmCompilerFreeTemp(cUnit, regCardNo);
45}
46
47static bool genConversionCall(CompilationUnit *cUnit, MIR *mir, void *funct,
48                                     int srcSize, int tgtSize)
49{
50    /*
51     * Don't optimize the register usage since it calls out to template
52     * functions
53     */
54    RegLocation rlSrc;
55    RegLocation rlDest;
56    int srcReg = 0;
57    int srcRegHi = 0;
58    dvmCompilerFlushAllRegs(cUnit);   /* Send everything to home location */
59
60    if (srcSize == kWord) {
61        srcReg = r_A0;
62    } else if (srcSize == kSingle) {
63#ifdef __mips_hard_float
64        srcReg = r_F12;
65#else
66        srcReg = r_A0;
67#endif
68    } else if (srcSize == kLong) {
69        srcReg = r_ARG0;
70        srcRegHi = r_ARG1;
71    } else if (srcSize == kDouble) {
72#ifdef __mips_hard_float
73        srcReg = r_FARG0;
74        srcRegHi = r_FARG1;
75#else
76        srcReg = r_ARG0;
77        srcRegHi = r_ARG1;
78#endif
79    }
80    else {
81        assert(0);
82    }
83
84    if (srcSize == kWord || srcSize == kSingle) {
85        rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
86        loadValueDirectFixed(cUnit, rlSrc, srcReg);
87    } else {
88        rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
89        loadValueDirectWideFixed(cUnit, rlSrc, srcReg, srcRegHi);
90    }
91    LOAD_FUNC_ADDR(cUnit, r_T9, (int)funct);
92    opReg(cUnit, kOpBlx, r_T9);
93    newLIR3(cUnit, kMipsLw, r_GP, STACK_OFFSET_GP, r_SP);
94    dvmCompilerClobberCallRegs(cUnit);
95    if (tgtSize == kWord || tgtSize == kSingle) {
96        RegLocation rlResult;
97        rlDest = dvmCompilerGetDest(cUnit, mir, 0);
98#ifdef __mips_hard_float
99        if (tgtSize == kSingle)
100            rlResult = dvmCompilerGetReturnAlt(cUnit);
101        else
102            rlResult = dvmCompilerGetReturn(cUnit);
103#else
104        rlResult = dvmCompilerGetReturn(cUnit);
105#endif
106        storeValue(cUnit, rlDest, rlResult);
107    } else {
108        RegLocation rlResult;
109        rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
110#ifdef __mips_hard_float
111        if (tgtSize == kDouble)
112            rlResult = dvmCompilerGetReturnWideAlt(cUnit);
113        else
114            rlResult = dvmCompilerGetReturnWide(cUnit);
115#else
116        rlResult = dvmCompilerGetReturnWide(cUnit);
117#endif
118        storeValueWide(cUnit, rlDest, rlResult);
119    }
120    return false;
121}
122
123
124static bool genArithOpFloatPortable(CompilationUnit *cUnit, MIR *mir,
125                                    RegLocation rlDest, RegLocation rlSrc1,
126                                    RegLocation rlSrc2)
127{
128    RegLocation rlResult;
129    void* funct;
130
131    switch (mir->dalvikInsn.opcode) {
132        case OP_ADD_FLOAT_2ADDR:
133        case OP_ADD_FLOAT:
134            funct = (void*) __addsf3;
135            break;
136        case OP_SUB_FLOAT_2ADDR:
137        case OP_SUB_FLOAT:
138            funct = (void*) __subsf3;
139            break;
140        case OP_DIV_FLOAT_2ADDR:
141        case OP_DIV_FLOAT:
142            funct = (void*) __divsf3;
143            break;
144        case OP_MUL_FLOAT_2ADDR:
145        case OP_MUL_FLOAT:
146            funct = (void*) __mulsf3;
147            break;
148        case OP_REM_FLOAT_2ADDR:
149        case OP_REM_FLOAT:
150            funct = (void*) fmodf;
151            break;
152        case OP_NEG_FLOAT: {
153            genNegFloat(cUnit, rlDest, rlSrc1);
154            return false;
155        }
156        default:
157            return true;
158    }
159
160    dvmCompilerFlushAllRegs(cUnit);   /* Send everything to home location */
161#ifdef __mips_hard_float
162    loadValueDirectFixed(cUnit, rlSrc1, r_F12);
163    loadValueDirectFixed(cUnit, rlSrc2, r_F14);
164#else
165    loadValueDirectFixed(cUnit, rlSrc1, r_A0);
166    loadValueDirectFixed(cUnit, rlSrc2, r_A1);
167#endif
168    LOAD_FUNC_ADDR(cUnit, r_T9, (int)funct);
169    opReg(cUnit, kOpBlx, r_T9);
170    newLIR3(cUnit, kMipsLw, r_GP, STACK_OFFSET_GP, r_SP);
171    dvmCompilerClobberCallRegs(cUnit);
172#ifdef __mips_hard_float
173    rlResult = dvmCompilerGetReturnAlt(cUnit);
174#else
175    rlResult = dvmCompilerGetReturn(cUnit);
176#endif
177    storeValue(cUnit, rlDest, rlResult);
178    return false;
179}
180
181static bool genArithOpDoublePortable(CompilationUnit *cUnit, MIR *mir,
182                                     RegLocation rlDest, RegLocation rlSrc1,
183                                     RegLocation rlSrc2)
184{
185    RegLocation rlResult;
186    void* funct;
187
188    switch (mir->dalvikInsn.opcode) {
189        case OP_ADD_DOUBLE_2ADDR:
190        case OP_ADD_DOUBLE:
191            funct = (void*) __adddf3;
192            break;
193        case OP_SUB_DOUBLE_2ADDR:
194        case OP_SUB_DOUBLE:
195            funct = (void*) __subdf3;
196            break;
197        case OP_DIV_DOUBLE_2ADDR:
198        case OP_DIV_DOUBLE:
199            funct = (void*) __divsf3;
200            break;
201        case OP_MUL_DOUBLE_2ADDR:
202        case OP_MUL_DOUBLE:
203            funct = (void*) __muldf3;
204            break;
205        case OP_REM_DOUBLE_2ADDR:
206        case OP_REM_DOUBLE:
207            funct = (void*) (double (*)(double, double)) fmod;
208            break;
209        case OP_NEG_DOUBLE: {
210            genNegDouble(cUnit, rlDest, rlSrc1);
211            return false;
212        }
213        default:
214            return true;
215    }
216    dvmCompilerFlushAllRegs(cUnit);   /* Send everything to home location */
217    LOAD_FUNC_ADDR(cUnit, r_T9, (int)funct);
218#ifdef __mips_hard_float
219    loadValueDirectWideFixed(cUnit, rlSrc1, r_F12, r_F13);
220    loadValueDirectWideFixed(cUnit, rlSrc2, r_F14, r_F15);
221#else
222    loadValueDirectWideFixed(cUnit, rlSrc1, r_ARG0, r_ARG1);
223    loadValueDirectWideFixed(cUnit, rlSrc2, r_ARG2, r_ARG3);
224#endif
225    opReg(cUnit, kOpBlx, r_T9);
226    newLIR3(cUnit, kMipsLw, r_GP, STACK_OFFSET_GP, r_SP);
227    dvmCompilerClobberCallRegs(cUnit);
228#ifdef __mips_hard_float
229    rlResult = dvmCompilerGetReturnWideAlt(cUnit);
230#else
231    rlResult = dvmCompilerGetReturnWide(cUnit);
232#endif
233    storeValueWide(cUnit, rlDest, rlResult);
234#if defined(WITH_SELF_VERIFICATION)
235    cUnit->usesLinkRegister = true;
236#endif
237    return false;
238}
239
240static bool genConversionPortable(CompilationUnit *cUnit, MIR *mir)
241{
242    Opcode opcode = mir->dalvikInsn.opcode;
243
244    switch (opcode) {
245        case OP_INT_TO_FLOAT:
246            return genConversionCall(cUnit, mir, (void*)__floatsisf, kWord, kSingle);
247        case OP_FLOAT_TO_INT:
248            return genConversionCall(cUnit, mir, (void*)__fixsfsi, kSingle, kWord);
249        case OP_DOUBLE_TO_FLOAT:
250            return genConversionCall(cUnit, mir, (void*)__truncdfsf2, kDouble, kSingle);
251        case OP_FLOAT_TO_DOUBLE:
252            return genConversionCall(cUnit, mir, (void*)__extendsfdf2, kSingle, kDouble);
253        case OP_INT_TO_DOUBLE:
254            return genConversionCall(cUnit, mir, (void*)__floatsidf, kWord, kDouble);
255        case OP_DOUBLE_TO_INT:
256            return genConversionCall(cUnit, mir, (void*)__fixdfsi, kDouble, kWord);
257        case OP_FLOAT_TO_LONG:
258            return genConversionCall(cUnit, mir, (void*)__fixsfdi, kSingle, kLong);
259        case OP_LONG_TO_FLOAT:
260            return genConversionCall(cUnit, mir, (void*)__floatdisf, kLong, kSingle);
261        case OP_DOUBLE_TO_LONG:
262            return genConversionCall(cUnit, mir, (void*)__fixdfdi, kDouble, kLong);
263        case OP_LONG_TO_DOUBLE:
264            return genConversionCall(cUnit, mir, (void*)__floatdidf, kLong, kDouble);
265        default:
266            return true;
267    }
268    return false;
269}
270
271#if defined(WITH_SELF_VERIFICATION)
272static void selfVerificationBranchInsert(LIR *currentLIR, Mipsopcode opcode,
273                          int dest, int src1)
274{
275assert(0); /* MIPSTODO port selfVerificationBranchInsert() */
276     MipsLIR *insn = (MipsLIR *) dvmCompilerNew(sizeof(MipsLIR), true);
277     insn->opcode = opcode;
278     insn->operands[0] = dest;
279     insn->operands[1] = src1;
280     setupResourceMasks(insn);
281     dvmCompilerInsertLIRBefore(currentLIR, (LIR *) insn);
282}
283
284/*
285 * Example where r14 (LR) is preserved around a heap access under
286 * self-verification mode in Thumb2:
287 *
288 * D/dalvikvm( 1538): 0x59414c5e (0026): ldr     r14, [r15pc, #220] <-hoisted
289 * D/dalvikvm( 1538): 0x59414c62 (002a): mla     r4, r0, r8, r4
290 * D/dalvikvm( 1538): 0x59414c66 (002e): adds    r3, r4, r3
291 * D/dalvikvm( 1538): 0x59414c6a (0032): push    <r5, r14>    ---+
292 * D/dalvikvm( 1538): 0x59414c6c (0034): blx_1   0x5940f494      |
293 * D/dalvikvm( 1538): 0x59414c6e (0036): blx_2   see above       <-MEM_OP_DECODE
294 * D/dalvikvm( 1538): 0x59414c70 (0038): ldr     r10, [r9, #0]   |
295 * D/dalvikvm( 1538): 0x59414c74 (003c): pop     <r5, r14>    ---+
296 * D/dalvikvm( 1538): 0x59414c78 (0040): mov     r11, r10
297 * D/dalvikvm( 1538): 0x59414c7a (0042): asr     r12, r11, #31
298 * D/dalvikvm( 1538): 0x59414c7e (0046): movs    r0, r2
299 * D/dalvikvm( 1538): 0x59414c80 (0048): movs    r1, r3
300 * D/dalvikvm( 1538): 0x59414c82 (004a): str     r2, [r5, #16]
301 * D/dalvikvm( 1538): 0x59414c84 (004c): mov     r2, r11
302 * D/dalvikvm( 1538): 0x59414c86 (004e): str     r3, [r5, #20]
303 * D/dalvikvm( 1538): 0x59414c88 (0050): mov     r3, r12
304 * D/dalvikvm( 1538): 0x59414c8a (0052): str     r11, [r5, #24]
305 * D/dalvikvm( 1538): 0x59414c8e (0056): str     r12, [r5, #28]
306 * D/dalvikvm( 1538): 0x59414c92 (005a): blx     r14             <-use of LR
307 *
308 */
309static void selfVerificationBranchInsertPass(CompilationUnit *cUnit)
310{
311assert(0); /* MIPSTODO port selfVerificationBranchInsertPass() */
312    MipsLIR *thisLIR;
313    Templateopcode opcode = TEMPLATE_MEM_OP_DECODE;
314
315    for (thisLIR = (MipsLIR *) cUnit->firstLIRInsn;
316         thisLIR != (MipsLIR *) cUnit->lastLIRInsn;
317         thisLIR = NEXT_LIR(thisLIR)) {
318        if (!thisLIR->flags.isNop && thisLIR->flags.insertWrapper) {
319            /*
320             * Push r5(FP) and r14(LR) onto stack. We need to make sure that
321             * SP is 8-byte aligned, and we use r5 as a temp to restore LR
322             * for Thumb-only target since LR cannot be directly accessed in
323             * Thumb mode. Another reason to choose r5 here is it is the Dalvik
324             * frame pointer and cannot be the target of the emulated heap
325             * load.
326             */
327            if (cUnit->usesLinkRegister) {
328                genSelfVerificationPreBranch(cUnit, thisLIR);
329            }
330
331            /* Branch to mem op decode template */
332            selfVerificationBranchInsert((LIR *) thisLIR, kThumbBlx1,
333                       (int) gDvmJit.codeCache + templateEntryOffsets[opcode],
334                       (int) gDvmJit.codeCache + templateEntryOffsets[opcode]);
335            selfVerificationBranchInsert((LIR *) thisLIR, kThumbBlx2,
336                       (int) gDvmJit.codeCache + templateEntryOffsets[opcode],
337                       (int) gDvmJit.codeCache + templateEntryOffsets[opcode]);
338
339            /* Restore LR */
340            if (cUnit->usesLinkRegister) {
341                genSelfVerificationPostBranch(cUnit, thisLIR);
342            }
343        }
344    }
345}
346#endif
347
348/* Generate conditional branch instructions */
349static MipsLIR *genConditionalBranchMips(CompilationUnit *cUnit,
350                                    MipsOpCode opc, int rs, int rt,
351                                    MipsLIR *target)
352{
353    MipsLIR *branch = opCompareBranch(cUnit, opc, rs, rt);
354    branch->generic.target = (LIR *) target;
355    return branch;
356}
357
358/* Generate a unconditional branch to go to the interpreter */
359static inline MipsLIR *genTrap(CompilationUnit *cUnit, int dOffset,
360                                  MipsLIR *pcrLabel)
361{
362    MipsLIR *branch = opNone(cUnit, kOpUncondBr);
363    return genCheckCommon(cUnit, dOffset, branch, pcrLabel);
364}
365
366/* Load a wide field from an object instance */
367static void genIGetWide(CompilationUnit *cUnit, MIR *mir, int fieldOffset)
368{
369    RegLocation rlObj = dvmCompilerGetSrc(cUnit, mir, 0);
370    RegLocation rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
371    RegLocation rlResult;
372    rlObj = loadValue(cUnit, rlObj, kCoreReg);
373    int regPtr = dvmCompilerAllocTemp(cUnit);
374
375    assert(rlDest.wide);
376
377    genNullCheck(cUnit, rlObj.sRegLow, rlObj.lowReg, mir->offset,
378                 NULL);/* null object? */
379    opRegRegImm(cUnit, kOpAdd, regPtr, rlObj.lowReg, fieldOffset);
380    rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true);
381
382    HEAP_ACCESS_SHADOW(true);
383    loadPair(cUnit, regPtr, rlResult.lowReg, rlResult.highReg);
384    HEAP_ACCESS_SHADOW(false);
385
386    dvmCompilerFreeTemp(cUnit, regPtr);
387    storeValueWide(cUnit, rlDest, rlResult);
388}
389
390/* Store a wide field to an object instance */
391static void genIPutWide(CompilationUnit *cUnit, MIR *mir, int fieldOffset)
392{
393    RegLocation rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
394    RegLocation rlObj = dvmCompilerGetSrc(cUnit, mir, 2);
395    rlObj = loadValue(cUnit, rlObj, kCoreReg);
396    int regPtr;
397    rlSrc = loadValueWide(cUnit, rlSrc, kAnyReg);
398    genNullCheck(cUnit, rlObj.sRegLow, rlObj.lowReg, mir->offset,
399                 NULL);/* null object? */
400    regPtr = dvmCompilerAllocTemp(cUnit);
401    opRegRegImm(cUnit, kOpAdd, regPtr, rlObj.lowReg, fieldOffset);
402
403    HEAP_ACCESS_SHADOW(true);
404    storePair(cUnit, regPtr, rlSrc.lowReg, rlSrc.highReg);
405    HEAP_ACCESS_SHADOW(false);
406
407    dvmCompilerFreeTemp(cUnit, regPtr);
408}
409
410/*
411 * Load a field from an object instance
412 *
413 */
414static void genIGet(CompilationUnit *cUnit, MIR *mir, OpSize size,
415                    int fieldOffset, bool isVolatile)
416{
417    RegLocation rlResult;
418    RegisterClass regClass = dvmCompilerRegClassBySize(size);
419    RegLocation rlObj = dvmCompilerGetSrc(cUnit, mir, 0);
420    RegLocation rlDest = dvmCompilerGetDest(cUnit, mir, 0);
421    rlObj = loadValue(cUnit, rlObj, kCoreReg);
422    rlResult = dvmCompilerEvalLoc(cUnit, rlDest, regClass, true);
423    genNullCheck(cUnit, rlObj.sRegLow, rlObj.lowReg, mir->offset,
424                 NULL);/* null object? */
425
426    HEAP_ACCESS_SHADOW(true);
427    loadBaseDisp(cUnit, mir, rlObj.lowReg, fieldOffset, rlResult.lowReg,
428                 size, rlObj.sRegLow);
429    HEAP_ACCESS_SHADOW(false);
430    if (isVolatile) {
431        dvmCompilerGenMemBarrier(cUnit, 0);
432    }
433
434    storeValue(cUnit, rlDest, rlResult);
435}
436
437/*
438 * Store a field to an object instance
439 *
440 */
441static void genIPut(CompilationUnit *cUnit, MIR *mir, OpSize size,
442                    int fieldOffset, bool isObject, bool isVolatile)
443{
444    RegisterClass regClass = dvmCompilerRegClassBySize(size);
445    RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
446    RegLocation rlObj = dvmCompilerGetSrc(cUnit, mir, 1);
447    rlObj = loadValue(cUnit, rlObj, kCoreReg);
448    rlSrc = loadValue(cUnit, rlSrc, regClass);
449    genNullCheck(cUnit, rlObj.sRegLow, rlObj.lowReg, mir->offset,
450                 NULL);/* null object? */
451
452    if (isVolatile) {
453        dvmCompilerGenMemBarrier(cUnit, 0);
454    }
455    HEAP_ACCESS_SHADOW(true);
456    storeBaseDisp(cUnit, rlObj.lowReg, fieldOffset, rlSrc.lowReg, size);
457    HEAP_ACCESS_SHADOW(false);
458    if (isVolatile) {
459        dvmCompilerGenMemBarrier(cUnit, 0);
460    }
461    if (isObject) {
462        /* NOTE: marking card based on object head */
463        markCard(cUnit, rlSrc.lowReg, rlObj.lowReg);
464    }
465}
466
467
468/*
469 * Generate array load
470 */
471static void genArrayGet(CompilationUnit *cUnit, MIR *mir, OpSize size,
472                        RegLocation rlArray, RegLocation rlIndex,
473                        RegLocation rlDest, int scale)
474{
475    RegisterClass regClass = dvmCompilerRegClassBySize(size);
476    int lenOffset = OFFSETOF_MEMBER(ArrayObject, length);
477    int dataOffset = OFFSETOF_MEMBER(ArrayObject, contents);
478    RegLocation rlResult;
479    rlArray = loadValue(cUnit, rlArray, kCoreReg);
480    rlIndex = loadValue(cUnit, rlIndex, kCoreReg);
481    int regPtr;
482
483    /* null object? */
484    MipsLIR * pcrLabel = NULL;
485
486    if (!(mir->OptimizationFlags & MIR_IGNORE_NULL_CHECK)) {
487        pcrLabel = genNullCheck(cUnit, rlArray.sRegLow,
488                                rlArray.lowReg, mir->offset, NULL);
489    }
490
491    regPtr = dvmCompilerAllocTemp(cUnit);
492
493    assert(IS_SIMM16(dataOffset));
494    if (scale) {
495        opRegRegImm(cUnit, kOpLsl, regPtr, rlIndex.lowReg, scale);
496    }
497
498    if (!(mir->OptimizationFlags & MIR_IGNORE_RANGE_CHECK)) {
499        int regLen = dvmCompilerAllocTemp(cUnit);
500        /* Get len */
501        loadWordDisp(cUnit, rlArray.lowReg, lenOffset, regLen);
502        genBoundsCheck(cUnit, rlIndex.lowReg, regLen, mir->offset,
503                       pcrLabel);
504        dvmCompilerFreeTemp(cUnit, regLen);
505    }
506
507    if (scale) {
508        opRegReg(cUnit, kOpAdd, regPtr, rlArray.lowReg);
509    } else {
510        opRegRegReg(cUnit, kOpAdd, regPtr, rlArray.lowReg, rlIndex.lowReg);
511    }
512
513    rlResult = dvmCompilerEvalLoc(cUnit, rlDest, regClass, true);
514    if ((size == kLong) || (size == kDouble)) {
515        HEAP_ACCESS_SHADOW(true);
516        loadBaseDispWide(cUnit, mir, regPtr, dataOffset, rlResult.lowReg,
517                         rlResult.highReg, INVALID_SREG);
518        HEAP_ACCESS_SHADOW(false);
519        dvmCompilerFreeTemp(cUnit, regPtr);
520        storeValueWide(cUnit, rlDest, rlResult);
521    } else {
522        HEAP_ACCESS_SHADOW(true);
523        loadBaseDisp(cUnit, mir, regPtr, dataOffset, rlResult.lowReg,
524                     size, INVALID_SREG);
525        HEAP_ACCESS_SHADOW(false);
526        dvmCompilerFreeTemp(cUnit, regPtr);
527        storeValue(cUnit, rlDest, rlResult);
528    }
529}
530
531/*
532 * Generate array store
533 *
534 */
535static void genArrayPut(CompilationUnit *cUnit, MIR *mir, OpSize size,
536                        RegLocation rlArray, RegLocation rlIndex,
537                        RegLocation rlSrc, int scale)
538{
539    RegisterClass regClass = dvmCompilerRegClassBySize(size);
540    int lenOffset = OFFSETOF_MEMBER(ArrayObject, length);
541    int dataOffset = OFFSETOF_MEMBER(ArrayObject, contents);
542
543    int regPtr;
544    rlArray = loadValue(cUnit, rlArray, kCoreReg);
545    rlIndex = loadValue(cUnit, rlIndex, kCoreReg);
546
547    if (dvmCompilerIsTemp(cUnit, rlArray.lowReg)) {
548        dvmCompilerClobber(cUnit, rlArray.lowReg);
549        regPtr = rlArray.lowReg;
550    } else {
551        regPtr = dvmCompilerAllocTemp(cUnit);
552        genRegCopy(cUnit, regPtr, rlArray.lowReg);
553    }
554
555    /* null object? */
556    MipsLIR * pcrLabel = NULL;
557
558    if (!(mir->OptimizationFlags & MIR_IGNORE_NULL_CHECK)) {
559        pcrLabel = genNullCheck(cUnit, rlArray.sRegLow, rlArray.lowReg,
560                                mir->offset, NULL);
561    }
562
563    assert(IS_SIMM16(dataOffset));
564    int tReg = dvmCompilerAllocTemp(cUnit);
565    if (scale) {
566        opRegRegImm(cUnit, kOpLsl, tReg, rlIndex.lowReg, scale);
567    }
568
569    if (!(mir->OptimizationFlags & MIR_IGNORE_RANGE_CHECK)) {
570        int regLen = dvmCompilerAllocTemp(cUnit);
571        //NOTE: max live temps(4) here.
572        /* Get len */
573        loadWordDisp(cUnit, rlArray.lowReg, lenOffset, regLen);
574        genBoundsCheck(cUnit, rlIndex.lowReg, regLen, mir->offset,
575                       pcrLabel);
576        dvmCompilerFreeTemp(cUnit, regLen);
577    }
578
579    if (scale) {
580        opRegReg(cUnit, kOpAdd, tReg, rlArray.lowReg);
581    } else {
582        opRegRegReg(cUnit, kOpAdd, tReg, rlArray.lowReg, rlIndex.lowReg);
583    }
584
585    /* at this point, tReg points to array, 2 live temps */
586    if ((size == kLong) || (size == kDouble)) {
587        rlSrc = loadValueWide(cUnit, rlSrc, regClass);
588        HEAP_ACCESS_SHADOW(true);
589        storeBaseDispWide(cUnit, tReg, dataOffset, rlSrc.lowReg, rlSrc.highReg)
590        HEAP_ACCESS_SHADOW(false);
591        dvmCompilerFreeTemp(cUnit, tReg);
592        dvmCompilerFreeTemp(cUnit, regPtr);
593    } else {
594        rlSrc = loadValue(cUnit, rlSrc, regClass);
595        HEAP_ACCESS_SHADOW(true);
596        storeBaseDisp(cUnit, tReg, dataOffset, rlSrc.lowReg, size);
597        dvmCompilerFreeTemp(cUnit, tReg);
598        HEAP_ACCESS_SHADOW(false);
599    }
600}
601
602/*
603 * Generate array object store
604 * Must use explicit register allocation here because of
605 * call-out to dvmCanPutArrayElement
606 */
607static void genArrayObjectPut(CompilationUnit *cUnit, MIR *mir,
608                              RegLocation rlArray, RegLocation rlIndex,
609                              RegLocation rlSrc, int scale)
610{
611    int lenOffset = OFFSETOF_MEMBER(ArrayObject, length);
612    int dataOffset = OFFSETOF_MEMBER(ArrayObject, contents);
613
614    int regLen = r_A0;
615    int regPtr = r_S0;  /* Preserved across call */
616    int regArray = r_A1;
617    int regIndex = r_S4;  /* Preserved across call */
618
619    dvmCompilerFlushAllRegs(cUnit);
620    // moved lock for r_S0 and r_S4 here from below since genBoundsCheck
621    // allocates a temporary that can result in clobbering either of them
622    dvmCompilerLockTemp(cUnit, regPtr);   // r_S0
623    dvmCompilerLockTemp(cUnit, regIndex); // r_S4
624
625    loadValueDirectFixed(cUnit, rlArray, regArray);
626    loadValueDirectFixed(cUnit, rlIndex, regIndex);
627
628    /* null object? */
629    MipsLIR * pcrLabel = NULL;
630
631    if (!(mir->OptimizationFlags & MIR_IGNORE_NULL_CHECK)) {
632        pcrLabel = genNullCheck(cUnit, rlArray.sRegLow, regArray,
633                                mir->offset, NULL);
634    }
635
636    if (!(mir->OptimizationFlags & MIR_IGNORE_RANGE_CHECK)) {
637        /* Get len */
638        loadWordDisp(cUnit, regArray, lenOffset, regLen);
639        /* regPtr -> array data */
640        opRegRegImm(cUnit, kOpAdd, regPtr, regArray, dataOffset);
641        genBoundsCheck(cUnit, regIndex, regLen, mir->offset,
642                       pcrLabel);
643    } else {
644        /* regPtr -> array data */
645        opRegRegImm(cUnit, kOpAdd, regPtr, regArray, dataOffset);
646    }
647
648    /* Get object to store */
649    loadValueDirectFixed(cUnit, rlSrc, r_A0);
650    LOAD_FUNC_ADDR(cUnit, r_T9, (int)dvmCanPutArrayElement);
651
652    /* Are we storing null?  If so, avoid check */
653    MipsLIR *branchOver = opCompareBranch(cUnit, kMipsBeqz, r_A0, -1);
654
655    /* Make sure the types are compatible */
656    loadWordDisp(cUnit, regArray, offsetof(Object, clazz), r_A1);
657    loadWordDisp(cUnit, r_A0, offsetof(Object, clazz), r_A0);
658    opReg(cUnit, kOpBlx, r_T9);
659    newLIR3(cUnit, kMipsLw, r_GP, STACK_OFFSET_GP, r_SP);
660    dvmCompilerClobberCallRegs(cUnit);
661
662    /*
663     * Using fixed registers here, and counting on r_S0 and r_S4 being
664     * preserved across the above call.  Tell the register allocation
665     * utilities about the regs we are using directly
666     */
667    dvmCompilerLockTemp(cUnit, r_A0);
668    dvmCompilerLockTemp(cUnit, r_A1);
669
670    /* Bad? - roll back and re-execute if so */
671    genRegImmCheck(cUnit, kMipsCondEq, r_V0, 0, mir->offset, pcrLabel);
672
673    /* Resume here - must reload element & array, regPtr & index preserved */
674    loadValueDirectFixed(cUnit, rlSrc, r_A0);
675    loadValueDirectFixed(cUnit, rlArray, r_A1);
676
677    MipsLIR *target = newLIR0(cUnit, kMipsPseudoTargetLabel);
678    target->defMask = ENCODE_ALL;
679    branchOver->generic.target = (LIR *) target;
680
681    HEAP_ACCESS_SHADOW(true);
682    storeBaseIndexed(cUnit, regPtr, regIndex, r_A0,
683                     scale, kWord);
684    HEAP_ACCESS_SHADOW(false);
685
686    dvmCompilerFreeTemp(cUnit, regPtr);
687    dvmCompilerFreeTemp(cUnit, regIndex);
688
689    /* NOTE: marking card here based on object head */
690    markCard(cUnit, r_A0, r_A1);
691}
692
693static bool genShiftOpLong(CompilationUnit *cUnit, MIR *mir,
694                           RegLocation rlDest, RegLocation rlSrc1,
695                           RegLocation rlShift)
696{
697    /*
698     * Don't mess with the regsiters here as there is a particular calling
699     * convention to the out-of-line handler.
700     */
701    RegLocation rlResult;
702
703    loadValueDirectWideFixed(cUnit, rlSrc1, r_ARG0, r_ARG1);
704    loadValueDirect(cUnit, rlShift, r_A2);
705    switch( mir->dalvikInsn.opcode) {
706        case OP_SHL_LONG:
707        case OP_SHL_LONG_2ADDR:
708            genDispatchToHandler(cUnit, TEMPLATE_SHL_LONG);
709            break;
710        case OP_SHR_LONG:
711        case OP_SHR_LONG_2ADDR:
712            genDispatchToHandler(cUnit, TEMPLATE_SHR_LONG);
713            break;
714        case OP_USHR_LONG:
715        case OP_USHR_LONG_2ADDR:
716            genDispatchToHandler(cUnit, TEMPLATE_USHR_LONG);
717            break;
718        default:
719            return true;
720    }
721    rlResult = dvmCompilerGetReturnWide(cUnit);
722    storeValueWide(cUnit, rlDest, rlResult);
723    return false;
724}
725
726static bool genArithOpLong(CompilationUnit *cUnit, MIR *mir,
727                           RegLocation rlDest, RegLocation rlSrc1,
728                           RegLocation rlSrc2)
729{
730    RegLocation rlResult;
731    OpKind firstOp = kOpBkpt;
732    OpKind secondOp = kOpBkpt;
733    bool callOut = false;
734    void *callTgt;
735
736    switch (mir->dalvikInsn.opcode) {
737        case OP_NOT_LONG:
738            rlSrc2 = loadValueWide(cUnit, rlSrc2, kCoreReg);
739            rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
740            opRegReg(cUnit, kOpMvn, rlResult.lowReg, rlSrc2.lowReg);
741            opRegReg(cUnit, kOpMvn, rlResult.highReg, rlSrc2.highReg);
742            storeValueWide(cUnit, rlDest, rlResult);
743            return false;
744            break;
745        case OP_ADD_LONG:
746        case OP_ADD_LONG_2ADDR:
747            firstOp = kOpAdd;
748            secondOp = kOpAdc;
749            break;
750        case OP_SUB_LONG:
751        case OP_SUB_LONG_2ADDR:
752            firstOp = kOpSub;
753            secondOp = kOpSbc;
754            break;
755        case OP_MUL_LONG:
756        case OP_MUL_LONG_2ADDR:
757            genMulLong(cUnit, rlDest, rlSrc1, rlSrc2);
758            return false;
759        case OP_DIV_LONG:
760        case OP_DIV_LONG_2ADDR:
761            callOut = true;
762            callTgt = (void*)__divdi3;
763            break;
764        case OP_REM_LONG:
765        case OP_REM_LONG_2ADDR:
766            callOut = true;
767            callTgt = (void*)__moddi3;
768            break;
769        case OP_AND_LONG_2ADDR:
770        case OP_AND_LONG:
771            firstOp = kOpAnd;
772            secondOp = kOpAnd;
773            break;
774        case OP_OR_LONG:
775        case OP_OR_LONG_2ADDR:
776            firstOp = kOpOr;
777            secondOp = kOpOr;
778            break;
779        case OP_XOR_LONG:
780        case OP_XOR_LONG_2ADDR:
781            firstOp = kOpXor;
782            secondOp = kOpXor;
783            break;
784        case OP_NEG_LONG: {
785            int tReg = dvmCompilerAllocTemp(cUnit);
786            rlSrc2 = loadValueWide(cUnit, rlSrc2, kCoreReg);
787            rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
788            newLIR3(cUnit, kMipsSubu, rlResult.lowReg, r_ZERO, rlSrc2.lowReg);
789            newLIR3(cUnit, kMipsSubu, tReg, r_ZERO, rlSrc2.highReg);
790            newLIR3(cUnit, kMipsSltu, rlResult.highReg, r_ZERO, rlResult.lowReg);
791            newLIR3(cUnit, kMipsSubu, rlResult.highReg, tReg, rlResult.highReg);
792            dvmCompilerFreeTemp(cUnit, tReg);
793            storeValueWide(cUnit, rlDest, rlResult);
794            return false;
795            break;
796        }
797        default:
798            LOGE("Invalid long arith op");
799            dvmCompilerAbort(cUnit);
800    }
801    if (!callOut) {
802        genLong3Addr(cUnit, mir, firstOp, secondOp, rlDest, rlSrc1, rlSrc2);
803    } else {
804        dvmCompilerFlushAllRegs(cUnit);   /* Send everything to home location */
805        loadValueDirectWideFixed(cUnit, rlSrc1, r_ARG0, r_ARG1);
806        LOAD_FUNC_ADDR(cUnit, r_T9, (int) callTgt);
807        loadValueDirectWideFixed(cUnit, rlSrc2, r_ARG2, r_ARG3);
808        opReg(cUnit, kOpBlx, r_T9);
809        newLIR3(cUnit, kMipsLw, r_GP, STACK_OFFSET_GP, r_SP);
810        dvmCompilerClobberCallRegs(cUnit);
811        rlResult = dvmCompilerGetReturnWide(cUnit);
812        storeValueWide(cUnit, rlDest, rlResult);
813#if defined(WITH_SELF_VERIFICATION)
814        cUnit->usesLinkRegister = true;
815#endif
816    }
817    return false;
818}
819
820static bool genArithOpInt(CompilationUnit *cUnit, MIR *mir,
821                          RegLocation rlDest, RegLocation rlSrc1,
822                          RegLocation rlSrc2)
823{
824    OpKind op = kOpBkpt;
825    bool checkZero = false;
826    bool unary = false;
827    RegLocation rlResult;
828    bool shiftOp = false;
829    int isDivRem = false;
830    MipsOpCode opc;
831    int divReg;
832
833    switch (mir->dalvikInsn.opcode) {
834        case OP_NEG_INT:
835            op = kOpNeg;
836            unary = true;
837            break;
838        case OP_NOT_INT:
839            op = kOpMvn;
840            unary = true;
841            break;
842        case OP_ADD_INT:
843        case OP_ADD_INT_2ADDR:
844            op = kOpAdd;
845            break;
846        case OP_SUB_INT:
847        case OP_SUB_INT_2ADDR:
848            op = kOpSub;
849            break;
850        case OP_MUL_INT:
851        case OP_MUL_INT_2ADDR:
852            op = kOpMul;
853            break;
854        case OP_DIV_INT:
855        case OP_DIV_INT_2ADDR:
856            isDivRem = true;
857            checkZero = true;
858            opc = kMipsMflo;
859            divReg = r_LO;
860            break;
861        case OP_REM_INT:
862        case OP_REM_INT_2ADDR:
863            isDivRem = true;
864            checkZero = true;
865            opc = kMipsMfhi;
866            divReg = r_HI;
867            break;
868        case OP_AND_INT:
869        case OP_AND_INT_2ADDR:
870            op = kOpAnd;
871            break;
872        case OP_OR_INT:
873        case OP_OR_INT_2ADDR:
874            op = kOpOr;
875            break;
876        case OP_XOR_INT:
877        case OP_XOR_INT_2ADDR:
878            op = kOpXor;
879            break;
880        case OP_SHL_INT:
881        case OP_SHL_INT_2ADDR:
882            shiftOp = true;
883            op = kOpLsl;
884            break;
885        case OP_SHR_INT:
886        case OP_SHR_INT_2ADDR:
887            shiftOp = true;
888            op = kOpAsr;
889            break;
890        case OP_USHR_INT:
891        case OP_USHR_INT_2ADDR:
892            shiftOp = true;
893            op = kOpLsr;
894            break;
895        default:
896            LOGE("Invalid word arith op: %#x(%d)",
897                 mir->dalvikInsn.opcode, mir->dalvikInsn.opcode);
898            dvmCompilerAbort(cUnit);
899    }
900
901    rlSrc1 = loadValue(cUnit, rlSrc1, kCoreReg);
902    if (unary) {
903        rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
904        opRegReg(cUnit, op, rlResult.lowReg,
905                 rlSrc1.lowReg);
906    } else if (isDivRem) {
907        rlSrc2 = loadValue(cUnit, rlSrc2, kCoreReg);
908        if (checkZero) {
909            genNullCheck(cUnit, rlSrc2.sRegLow, rlSrc2.lowReg, mir->offset, NULL);
910        }
911        newLIR4(cUnit, kMipsDiv, r_HI, r_LO, rlSrc1.lowReg, rlSrc2.lowReg);
912        rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
913        newLIR2(cUnit, opc, rlResult.lowReg, divReg);
914    } else {
915        rlSrc2 = loadValue(cUnit, rlSrc2, kCoreReg);
916        if (shiftOp) {
917            int tReg = dvmCompilerAllocTemp(cUnit);
918            opRegRegImm(cUnit, kOpAnd, tReg, rlSrc2.lowReg, 31);
919            rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
920            opRegRegReg(cUnit, op, rlResult.lowReg,
921                        rlSrc1.lowReg, tReg);
922            dvmCompilerFreeTemp(cUnit, tReg);
923        } else {
924            rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
925            opRegRegReg(cUnit, op, rlResult.lowReg,
926                        rlSrc1.lowReg, rlSrc2.lowReg);
927        }
928    }
929    storeValue(cUnit, rlDest, rlResult);
930
931    return false;
932}
933
934static bool genArithOp(CompilationUnit *cUnit, MIR *mir)
935{
936    Opcode opcode = mir->dalvikInsn.opcode;
937    RegLocation rlDest;
938    RegLocation rlSrc1;
939    RegLocation rlSrc2;
940    /* Deduce sizes of operands */
941    if (mir->ssaRep->numUses == 2) {
942        rlSrc1 = dvmCompilerGetSrc(cUnit, mir, 0);
943        rlSrc2 = dvmCompilerGetSrc(cUnit, mir, 1);
944    } else if (mir->ssaRep->numUses == 3) {
945        rlSrc1 = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
946        rlSrc2 = dvmCompilerGetSrc(cUnit, mir, 2);
947    } else {
948        rlSrc1 = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
949        rlSrc2 = dvmCompilerGetSrcWide(cUnit, mir, 2, 3);
950        assert(mir->ssaRep->numUses == 4);
951    }
952    if (mir->ssaRep->numDefs == 1) {
953        rlDest = dvmCompilerGetDest(cUnit, mir, 0);
954    } else {
955        assert(mir->ssaRep->numDefs == 2);
956        rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
957    }
958
959    if ((opcode >= OP_ADD_LONG_2ADDR) && (opcode <= OP_XOR_LONG_2ADDR)) {
960        return genArithOpLong(cUnit,mir, rlDest, rlSrc1, rlSrc2);
961    }
962    if ((opcode >= OP_ADD_LONG) && (opcode <= OP_XOR_LONG)) {
963        return genArithOpLong(cUnit,mir, rlDest, rlSrc1, rlSrc2);
964    }
965    if ((opcode >= OP_SHL_LONG_2ADDR) && (opcode <= OP_USHR_LONG_2ADDR)) {
966        return genShiftOpLong(cUnit,mir, rlDest, rlSrc1, rlSrc2);
967    }
968    if ((opcode >= OP_SHL_LONG) && (opcode <= OP_USHR_LONG)) {
969        return genShiftOpLong(cUnit,mir, rlDest, rlSrc1, rlSrc2);
970    }
971    if ((opcode >= OP_ADD_INT_2ADDR) && (opcode <= OP_USHR_INT_2ADDR)) {
972        return genArithOpInt(cUnit,mir, rlDest, rlSrc1, rlSrc2);
973    }
974    if ((opcode >= OP_ADD_INT) && (opcode <= OP_USHR_INT)) {
975        return genArithOpInt(cUnit,mir, rlDest, rlSrc1, rlSrc2);
976    }
977    if ((opcode >= OP_ADD_FLOAT_2ADDR) && (opcode <= OP_REM_FLOAT_2ADDR)) {
978        return genArithOpFloat(cUnit,mir, rlDest, rlSrc1, rlSrc2);
979    }
980    if ((opcode >= OP_ADD_FLOAT) && (opcode <= OP_REM_FLOAT)) {
981        return genArithOpFloat(cUnit, mir, rlDest, rlSrc1, rlSrc2);
982    }
983    if ((opcode >= OP_ADD_DOUBLE_2ADDR) && (opcode <= OP_REM_DOUBLE_2ADDR)) {
984        return genArithOpDouble(cUnit,mir, rlDest, rlSrc1, rlSrc2);
985    }
986    if ((opcode >= OP_ADD_DOUBLE) && (opcode <= OP_REM_DOUBLE)) {
987        return genArithOpDouble(cUnit,mir, rlDest, rlSrc1, rlSrc2);
988    }
989    return true;
990}
991
992/* Generate unconditional branch instructions */
993static MipsLIR *genUnconditionalBranch(CompilationUnit *cUnit, MipsLIR *target)
994{
995    MipsLIR *branch = opNone(cUnit, kOpUncondBr);
996    branch->generic.target = (LIR *) target;
997    return branch;
998}
999
1000/* Perform the actual operation for OP_RETURN_* */
1001void genReturnCommon(CompilationUnit *cUnit, MIR *mir)
1002{
1003    genDispatchToHandler(cUnit, gDvmJit.methodTraceSupport ?
1004                         TEMPLATE_RETURN_PROF : TEMPLATE_RETURN);
1005#if defined(WITH_JIT_TUNING)
1006    gDvmJit.returnOp++;
1007#endif
1008    int dPC = (int) (cUnit->method->insns + mir->offset);
1009    /* Insert branch, but defer setting of target */
1010    MipsLIR *branch = genUnconditionalBranch(cUnit, NULL);
1011    /* Set up the place holder to reconstruct this Dalvik PC */
1012    MipsLIR *pcrLabel = (MipsLIR *) dvmCompilerNew(sizeof(MipsLIR), true);
1013    pcrLabel->opcode = kMipsPseudoPCReconstructionCell;
1014    pcrLabel->operands[0] = dPC;
1015    pcrLabel->operands[1] = mir->offset;
1016    /* Insert the place holder to the growable list */
1017    dvmInsertGrowableList(&cUnit->pcReconstructionList, (intptr_t) pcrLabel);
1018    /* Branch to the PC reconstruction code */
1019    branch->generic.target = (LIR *) pcrLabel;
1020}
1021
1022static void genProcessArgsNoRange(CompilationUnit *cUnit, MIR *mir,
1023                                  DecodedInstruction *dInsn,
1024                                  MipsLIR **pcrLabel)
1025{
1026    unsigned int i;
1027    unsigned int regMask = 0;
1028    RegLocation rlArg;
1029    int numDone = 0;
1030
1031    /*
1032     * Load arguments to r_A0..r_T0.  Note that these registers may contain
1033     * live values, so we clobber them immediately after loading to prevent
1034     * them from being used as sources for subsequent loads.
1035     */
1036    dvmCompilerLockAllTemps(cUnit);
1037    for (i = 0; i < dInsn->vA; i++) {
1038        regMask |= 1 << i;
1039        rlArg = dvmCompilerGetSrc(cUnit, mir, numDone++);
1040        loadValueDirectFixed(cUnit, rlArg, i+r_A0); /* r_A0 thru r_T0 */
1041    }
1042    if (regMask) {
1043        /* Up to 5 args are pushed on top of FP - sizeofStackSaveArea */
1044        opRegRegImm(cUnit, kOpSub, r_S4, rFP,
1045                    sizeof(StackSaveArea) + (dInsn->vA << 2));
1046        /* generate null check */
1047        if (pcrLabel) {
1048            *pcrLabel = genNullCheck(cUnit, dvmCompilerSSASrc(mir, 0), r_A0,
1049                                     mir->offset, NULL);
1050        }
1051        storeMultiple(cUnit, r_S4, regMask);
1052    }
1053}
1054
1055static void genProcessArgsRange(CompilationUnit *cUnit, MIR *mir,
1056                                DecodedInstruction *dInsn,
1057                                MipsLIR **pcrLabel)
1058{
1059    int srcOffset = dInsn->vC << 2;
1060    int numArgs = dInsn->vA;
1061    int regMask;
1062
1063    /*
1064     * Note: here, all promoted registers will have been flushed
1065     * back to the Dalvik base locations, so register usage restrictins
1066     * are lifted.  All parms loaded from original Dalvik register
1067     * region - even though some might conceivably have valid copies
1068     * cached in a preserved register.
1069     */
1070    dvmCompilerLockAllTemps(cUnit);
1071
1072    /*
1073     * r4PC     : &rFP[vC]
1074     * r_S4: &newFP[0]
1075     */
1076    opRegRegImm(cUnit, kOpAdd, r4PC, rFP, srcOffset);
1077    /* load [r_A0 up to r_A3)] */
1078    regMask = (1 << ((numArgs < 4) ? numArgs : 4)) - 1;
1079    /*
1080     * Protect the loadMultiple instruction from being reordered with other
1081     * Dalvik stack accesses.
1082     *
1083     * This code is also shared by the invoke jumbo instructions, and this
1084     * does not need to be done if the invoke jumbo has no arguments.
1085     */
1086    if (numArgs != 0) loadMultiple(cUnit, r4PC, regMask);
1087
1088    opRegRegImm(cUnit, kOpSub, r_S4, rFP,
1089                sizeof(StackSaveArea) + (numArgs << 2));
1090    /* generate null check */
1091    if (pcrLabel) {
1092        *pcrLabel = genNullCheck(cUnit, dvmCompilerSSASrc(mir, 0), r_A0,
1093                                 mir->offset, NULL);
1094    }
1095
1096    /*
1097     * Handle remaining 4n arguments:
1098     * store previously loaded 4 values and load the next 4 values
1099     */
1100    if (numArgs >= 8) {
1101        MipsLIR *loopLabel = NULL;
1102        /*
1103         * r_A0 contains "this" and it will be used later, so push it to the stack
1104         * first. Pushing r_S1 (rFP) is just for stack alignment purposes.
1105         */
1106
1107        newLIR2(cUnit, kMipsMove, r_T0, r_A0);
1108        newLIR2(cUnit, kMipsMove, r_T1, r_S1);
1109
1110        /* No need to generate the loop structure if numArgs <= 11 */
1111        if (numArgs > 11) {
1112            loadConstant(cUnit, rFP, ((numArgs - 4) >> 2) << 2);
1113            loopLabel = newLIR0(cUnit, kMipsPseudoTargetLabel);
1114            loopLabel->defMask = ENCODE_ALL;
1115        }
1116        storeMultiple(cUnit, r_S4, regMask);
1117        /*
1118         * Protect the loadMultiple instruction from being reordered with other
1119         * Dalvik stack accesses.
1120         */
1121        loadMultiple(cUnit, r4PC, regMask);
1122        /* No need to generate the loop structure if numArgs <= 11 */
1123        if (numArgs > 11) {
1124            opRegImm(cUnit, kOpSub, rFP, 4);
1125            genConditionalBranchMips(cUnit, kMipsBne, rFP, r_ZERO, loopLabel);
1126        }
1127    }
1128
1129    /* Save the last batch of loaded values */
1130    if (numArgs != 0) storeMultiple(cUnit, r_S4, regMask);
1131
1132    /* Generate the loop epilogue - don't use r_A0 */
1133    if ((numArgs > 4) && (numArgs % 4)) {
1134        regMask = ((1 << (numArgs & 0x3)) - 1) << 1;
1135        /*
1136         * Protect the loadMultiple instruction from being reordered with other
1137         * Dalvik stack accesses.
1138         */
1139        loadMultiple(cUnit, r4PC, regMask);
1140    }
1141    if (numArgs >= 8) {
1142        newLIR2(cUnit, kMipsMove, r_A0, r_T0);
1143        newLIR2(cUnit, kMipsMove, r_S1, r_T1);
1144    }
1145
1146    /* Save the modulo 4 arguments */
1147    if ((numArgs > 4) && (numArgs % 4)) {
1148        storeMultiple(cUnit, r_S4, regMask);
1149    }
1150}
1151
1152/*
1153 * Generate code to setup the call stack then jump to the chaining cell if it
1154 * is not a native method.
1155 */
1156static void genInvokeSingletonCommon(CompilationUnit *cUnit, MIR *mir,
1157                                     BasicBlock *bb, MipsLIR *labelList,
1158                                     MipsLIR *pcrLabel,
1159                                     const Method *calleeMethod)
1160{
1161    /*
1162     * Note: all Dalvik register state should be flushed to
1163     * memory by the point, so register usage restrictions no
1164     * longer apply.  All temp & preserved registers may be used.
1165     */
1166    dvmCompilerLockAllTemps(cUnit);
1167    MipsLIR *retChainingCell = &labelList[bb->fallThrough->id];
1168
1169    /* r_A1 = &retChainingCell */
1170    dvmCompilerLockTemp(cUnit, r_A1);
1171    MipsLIR *addrRetChain = newLIR2(cUnit, kMipsLahi, r_A1, 0);
1172    addrRetChain->generic.target = (LIR *) retChainingCell;
1173    addrRetChain = newLIR3(cUnit, kMipsLalo, r_A1, r_A1, 0);
1174    addrRetChain->generic.target = (LIR *) retChainingCell;
1175
1176    /* r4PC = dalvikCallsite */
1177    loadConstant(cUnit, r4PC,
1178                 (int) (cUnit->method->insns + mir->offset));
1179    /*
1180     * r_A0 = calleeMethod (loaded upon calling genInvokeSingletonCommon)
1181     * r_A1 = &ChainingCell
1182     * r4PC = callsiteDPC
1183     */
1184    if (dvmIsNativeMethod(calleeMethod)) {
1185        genDispatchToHandler(cUnit, gDvmJit.methodTraceSupport ?
1186            TEMPLATE_INVOKE_METHOD_NATIVE_PROF :
1187            TEMPLATE_INVOKE_METHOD_NATIVE);
1188#if defined(WITH_JIT_TUNING)
1189        gDvmJit.invokeNative++;
1190#endif
1191    } else {
1192        genDispatchToHandler(cUnit, gDvmJit.methodTraceSupport ?
1193            TEMPLATE_INVOKE_METHOD_CHAIN_PROF :
1194            TEMPLATE_INVOKE_METHOD_CHAIN);
1195#if defined(WITH_JIT_TUNING)
1196        gDvmJit.invokeMonomorphic++;
1197#endif
1198        /* Branch to the chaining cell */
1199        genUnconditionalBranch(cUnit, &labelList[bb->taken->id]);
1200    }
1201    /* Handle exceptions using the interpreter */
1202    genTrap(cUnit, mir->offset, pcrLabel);
1203}
1204
1205/*
1206 * Generate code to check the validity of a predicted chain and take actions
1207 * based on the result.
1208 *
1209 * 0x2f1304c4 :  lui      s0,0x2d22(11554)            # s0 <- dalvikPC
1210 * 0x2f1304c8 :  ori      s0,s0,0x2d22848c(757236876)
1211 * 0x2f1304cc :  lahi/lui a1,0x2f13(12051)            # a1 <- &retChainingCell
1212 * 0x2f1304d0 :  lalo/ori a1,a1,0x2f13055c(789775708)
1213 * 0x2f1304d4 :  lahi/lui a2,0x2f13(12051)            # a2 <- &predictedChainingCell
1214 * 0x2f1304d8 :  lalo/ori a2,a2,0x2f13056c(789775724)
1215 * 0x2f1304dc :  jal      0x2f12d1ec(789762540)       # call TEMPLATE_INVOKE_METHOD_PREDICTED_CHAIN
1216 * 0x2f1304e0 :  nop
1217 * 0x2f1304e4 :  b        0x2f13056c (L0x11ec10)      # off to the predicted chain
1218 * 0x2f1304e8 :  nop
1219 * 0x2f1304ec :  b        0x2f13054c (L0x11fc80)      # punt to the interpreter
1220 * 0x2f1304f0 :  lui      a0,0x2d22(11554)
1221 * 0x2f1304f4 :  lw       a0,156(s4)                  # a0 <- this->class->vtable[methodIdx]
1222 * 0x2f1304f8 :  bgtz     a1,0x2f13051c (L0x11fa40)   # if >0 don't rechain
1223 * 0x2f1304fc :  nop
1224 * 0x2f130500 :  lui      t9,0x2aba(10938)
1225 * 0x2f130504 :  ori      t9,t9,0x2abae3f8(716891128)
1226 * 0x2f130508 :  move     a1,s2
1227 * 0x2f13050c :  jalr     ra,t9                       # call dvmJitToPatchPredictedChain
1228 * 0x2f130510 :  nop
1229 * 0x2f130514 :  lw       gp,84(sp)
1230 * 0x2f130518 :  move     a0,v0
1231 * 0x2f13051c :  lahi/lui a1,0x2f13(12051)            # a1 <- &retChainingCell
1232 * 0x2f130520 :  lalo/ori a1,a1,0x2f13055c(789775708)
1233 * 0x2f130524 :  jal      0x2f12d0c4(789762244)       # call TEMPLATE_INVOKE_METHOD_NO_OPT
1234 * 0x2f130528 :  nop
1235 */
1236static void genInvokeVirtualCommon(CompilationUnit *cUnit, MIR *mir,
1237                                   int methodIndex,
1238                                   MipsLIR *retChainingCell,
1239                                   MipsLIR *predChainingCell,
1240                                   MipsLIR *pcrLabel)
1241{
1242    /*
1243     * Note: all Dalvik register state should be flushed to
1244     * memory by the point, so register usage restrictions no
1245     * longer apply.  Lock temps to prevent them from being
1246     * allocated by utility routines.
1247     */
1248    dvmCompilerLockAllTemps(cUnit);
1249
1250    /*
1251     * For verbose printing, store the method pointer in operands[1] first as
1252     * operands[0] will be clobbered in dvmCompilerMIR2LIR.
1253     */
1254    predChainingCell->operands[1] = (int) mir->meta.callsiteInfo->method;
1255
1256    /* "this" is already left in r_A0 by genProcessArgs* */
1257
1258    /* r4PC = dalvikCallsite */
1259    loadConstant(cUnit, r4PC,
1260                 (int) (cUnit->method->insns + mir->offset));
1261
1262    /* r_A1 = &retChainingCell */
1263    MipsLIR *addrRetChain = newLIR2(cUnit, kMipsLahi, r_A1, 0);
1264    addrRetChain->generic.target = (LIR *) retChainingCell;
1265    addrRetChain = newLIR3(cUnit, kMipsLalo, r_A1, r_A1, 0);
1266    addrRetChain->generic.target = (LIR *) retChainingCell;
1267
1268    /* r_A2 = &predictedChainingCell */
1269    MipsLIR *predictedChainingCell = newLIR2(cUnit, kMipsLahi, r_A2, 0);
1270    predictedChainingCell->generic.target = (LIR *) predChainingCell;
1271    predictedChainingCell = newLIR3(cUnit, kMipsLalo, r_A2, r_A2, 0);
1272    predictedChainingCell->generic.target = (LIR *) predChainingCell;
1273
1274    genDispatchToHandler(cUnit, gDvmJit.methodTraceSupport ?
1275        TEMPLATE_INVOKE_METHOD_PREDICTED_CHAIN_PROF :
1276        TEMPLATE_INVOKE_METHOD_PREDICTED_CHAIN);
1277
1278    /* return through ra - jump to the chaining cell */
1279    genUnconditionalBranch(cUnit, predChainingCell);
1280
1281    /*
1282     * null-check on "this" may have been eliminated, but we still need a PC-
1283     * reconstruction label for stack overflow bailout.
1284     */
1285    if (pcrLabel == NULL) {
1286        int dPC = (int) (cUnit->method->insns + mir->offset);
1287        pcrLabel = (MipsLIR *) dvmCompilerNew(sizeof(MipsLIR), true);
1288        pcrLabel->opcode = kMipsPseudoPCReconstructionCell;
1289        pcrLabel->operands[0] = dPC;
1290        pcrLabel->operands[1] = mir->offset;
1291        /* Insert the place holder to the growable list */
1292        dvmInsertGrowableList(&cUnit->pcReconstructionList,
1293                              (intptr_t) pcrLabel);
1294    }
1295
1296    /* return through ra+8 - punt to the interpreter */
1297    genUnconditionalBranch(cUnit, pcrLabel);
1298
1299    /*
1300     * return through ra+16 - fully resolve the callee method.
1301     * r_A1 <- count
1302     * r_A2 <- &predictedChainCell
1303     * r_A3 <- this->class
1304     * r4 <- dPC
1305     * r_S4 <- this->class->vtable
1306     */
1307
1308    /* r_A0 <- calleeMethod */
1309    loadWordDisp(cUnit, r_S4, methodIndex * 4, r_A0);
1310
1311    /* Check if rechain limit is reached */
1312    MipsLIR *bypassRechaining = opCompareBranch(cUnit, kMipsBgtz, r_A1, -1);
1313
1314    LOAD_FUNC_ADDR(cUnit, r_T9, (int) dvmJitToPatchPredictedChain);
1315
1316    genRegCopy(cUnit, r_A1, rSELF);
1317
1318    /*
1319     * r_A0 = calleeMethod
1320     * r_A2 = &predictedChainingCell
1321     * r_A3 = class
1322     *
1323     * &returnChainingCell has been loaded into r_A1 but is not needed
1324     * when patching the chaining cell and will be clobbered upon
1325     * returning so it will be reconstructed again.
1326     */
1327    opReg(cUnit, kOpBlx, r_T9);
1328    newLIR3(cUnit, kMipsLw, r_GP, STACK_OFFSET_GP, r_SP);
1329    newLIR2(cUnit, kMipsMove, r_A0, r_V0);
1330
1331    /* r_A1 = &retChainingCell */
1332    addrRetChain = newLIR2(cUnit, kMipsLahi, r_A1, 0);
1333    addrRetChain->generic.target = (LIR *) retChainingCell;
1334    bypassRechaining->generic.target = (LIR *) addrRetChain;
1335    addrRetChain = newLIR3(cUnit, kMipsLalo, r_A1, r_A1, 0);
1336    addrRetChain->generic.target = (LIR *) retChainingCell;
1337
1338    /*
1339     * r_A0 = calleeMethod,
1340     * r_A1 = &ChainingCell,
1341     * r4PC = callsiteDPC,
1342     */
1343    genDispatchToHandler(cUnit, gDvmJit.methodTraceSupport ?
1344        TEMPLATE_INVOKE_METHOD_NO_OPT_PROF :
1345        TEMPLATE_INVOKE_METHOD_NO_OPT);
1346#if defined(WITH_JIT_TUNING)
1347    gDvmJit.invokePolymorphic++;
1348#endif
1349    /* Handle exceptions using the interpreter */
1350    genTrap(cUnit, mir->offset, pcrLabel);
1351}
1352
1353/* "this" pointer is already in r0 */
1354static void genInvokeVirtualWholeMethod(CompilationUnit *cUnit,
1355                                        MIR *mir,
1356                                        void *calleeAddr,
1357                                        MipsLIR *retChainingCell)
1358{
1359    CallsiteInfo *callsiteInfo = mir->meta.callsiteInfo;
1360    dvmCompilerLockAllTemps(cUnit);
1361
1362    loadClassPointer(cUnit, r_A1, (int) callsiteInfo);
1363
1364    loadWordDisp(cUnit, r_A0, offsetof(Object, clazz), r_A2);
1365    /*
1366     * Set the misPredBranchOver target so that it will be generated when the
1367     * code for the non-optimized invoke is generated.
1368     */
1369    /* Branch to the slow path if classes are not equal */
1370    MipsLIR *classCheck = opCompareBranch(cUnit, kMipsBne, r_A1, r_A2);
1371
1372    /* a0 = the Dalvik PC of the callsite */
1373    loadConstant(cUnit, r_A0, (int) (cUnit->method->insns + mir->offset));
1374
1375    newLIR1(cUnit, kMipsJal, (int) calleeAddr);
1376    genUnconditionalBranch(cUnit, retChainingCell);
1377
1378    /* Target of slow path */
1379    MipsLIR *slowPathLabel = newLIR0(cUnit, kMipsPseudoTargetLabel);
1380
1381    slowPathLabel->defMask = ENCODE_ALL;
1382    classCheck->generic.target = (LIR *) slowPathLabel;
1383
1384    // FIXME
1385    cUnit->printMe = true;
1386}
1387
1388static void genInvokeSingletonWholeMethod(CompilationUnit *cUnit,
1389                                          MIR *mir,
1390                                          void *calleeAddr,
1391                                          MipsLIR *retChainingCell)
1392{
1393    /* a0 = the Dalvik PC of the callsite */
1394    loadConstant(cUnit, r_A0, (int) (cUnit->method->insns + mir->offset));
1395
1396    newLIR1(cUnit, kMipsJal, (int) calleeAddr);
1397    genUnconditionalBranch(cUnit, retChainingCell);
1398
1399    // FIXME
1400    cUnit->printMe = true;
1401}
1402
1403/* Geneate a branch to go back to the interpreter */
1404static void genPuntToInterp(CompilationUnit *cUnit, unsigned int offset)
1405{
1406    /* a0 = dalvik pc */
1407    dvmCompilerFlushAllRegs(cUnit);
1408    loadConstant(cUnit, r_A0, (int) (cUnit->method->insns + offset));
1409#if 0 /* MIPSTODO tempoary workaround unaligned access on sigma hardware
1410             this can removed when we're not punting to genInterpSingleStep
1411             for opcodes that haven't been activated yet */
1412    loadWordDisp(cUnit, r_A0, offsetof(Object, clazz), r_A3);
1413#endif
1414    loadWordDisp(cUnit, rSELF, offsetof(Thread,
1415                 jitToInterpEntries.dvmJitToInterpPunt), r_A1);
1416
1417    opReg(cUnit, kOpBlx, r_A1);
1418}
1419
1420/*
1421 * Attempt to single step one instruction using the interpreter and return
1422 * to the compiled code for the next Dalvik instruction
1423 */
1424static void genInterpSingleStep(CompilationUnit *cUnit, MIR *mir)
1425{
1426    int flags = dexGetFlagsFromOpcode(mir->dalvikInsn.opcode);
1427    int flagsToCheck = kInstrCanBranch | kInstrCanSwitch | kInstrCanReturn;
1428
1429    // Single stepping is considered loop mode breaker
1430    if (cUnit->jitMode == kJitLoop) {
1431        cUnit->quitLoopMode = true;
1432        return;
1433    }
1434
1435    //If already optimized out, just ignore
1436    if (mir->dalvikInsn.opcode == OP_NOP)
1437        return;
1438
1439    //Ugly, but necessary.  Flush all Dalvik regs so Interp can find them
1440    dvmCompilerFlushAllRegs(cUnit);
1441
1442    if ((mir->next == NULL) || (flags & flagsToCheck)) {
1443       genPuntToInterp(cUnit, mir->offset);
1444       return;
1445    }
1446    int entryAddr = offsetof(Thread,
1447                             jitToInterpEntries.dvmJitToInterpSingleStep);
1448    loadWordDisp(cUnit, rSELF, entryAddr, r_A2);
1449    /* a0 = dalvik pc */
1450    loadConstant(cUnit, r_A0, (int) (cUnit->method->insns + mir->offset));
1451    /* a1 = dalvik pc of following instruction */
1452    loadConstant(cUnit, r_A1, (int) (cUnit->method->insns + mir->next->offset));
1453    opReg(cUnit, kOpBlx, r_A2);
1454}
1455
1456/*
1457 * To prevent a thread in a monitor wait from blocking the Jit from
1458 * resetting the code cache, heavyweight monitor lock will not
1459 * be allowed to return to an existing translation.  Instead, we will
1460 * handle them by branching to a handler, which will in turn call the
1461 * runtime lock routine and then branch directly back to the
1462 * interpreter main loop.  Given the high cost of the heavyweight
1463 * lock operation, this additional cost should be slight (especially when
1464 * considering that we expect the vast majority of lock operations to
1465 * use the fast-path thin lock bypass).
1466 */
1467static void genMonitorPortable(CompilationUnit *cUnit, MIR *mir)
1468{
1469    bool isEnter = (mir->dalvikInsn.opcode == OP_MONITOR_ENTER);
1470    genExportPC(cUnit, mir);
1471    dvmCompilerFlushAllRegs(cUnit);   /* Send everything to home location */
1472    RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
1473    loadValueDirectFixed(cUnit, rlSrc, r_A1);
1474    genRegCopy(cUnit, r_A0, rSELF);
1475    genNullCheck(cUnit, rlSrc.sRegLow, r_A1, mir->offset, NULL);
1476    if (isEnter) {
1477        /* Get dPC of next insn */
1478        loadConstant(cUnit, r4PC, (int)(cUnit->method->insns + mir->offset +
1479                 dexGetWidthFromOpcode(OP_MONITOR_ENTER)));
1480        genDispatchToHandler(cUnit, TEMPLATE_MONITOR_ENTER);
1481    } else {
1482        LOAD_FUNC_ADDR(cUnit, r_T9, (int)dvmUnlockObject);
1483        /* Do the call */
1484        opReg(cUnit, kOpBlx, r_T9);
1485        newLIR3(cUnit, kMipsLw, r_GP, STACK_OFFSET_GP, r_SP);
1486        /* Did we throw? */
1487        MipsLIR *branchOver = opCompareBranch(cUnit, kMipsBne, r_V0, r_ZERO);
1488        loadConstant(cUnit, r_A0,
1489                     (int) (cUnit->method->insns + mir->offset +
1490                     dexGetWidthFromOpcode(OP_MONITOR_EXIT)));
1491        genDispatchToHandler(cUnit, TEMPLATE_THROW_EXCEPTION_COMMON);
1492        MipsLIR *target = newLIR0(cUnit, kMipsPseudoTargetLabel);
1493        target->defMask = ENCODE_ALL;
1494        branchOver->generic.target = (LIR *) target;
1495        dvmCompilerClobberCallRegs(cUnit);
1496    }
1497}
1498/*#endif*/
1499
1500/*
1501 * Fetch *self->info.breakFlags. If the breakFlags are non-zero,
1502 * punt to the interpreter.
1503 */
1504static void genSuspendPoll(CompilationUnit *cUnit, MIR *mir)
1505{
1506    int rTemp = dvmCompilerAllocTemp(cUnit);
1507    MipsLIR *ld;
1508    ld = loadBaseDisp(cUnit, NULL, rSELF,
1509                      offsetof(Thread, interpBreak.ctl.breakFlags),
1510                      rTemp, kUnsignedByte, INVALID_SREG);
1511    setMemRefType(ld, true /* isLoad */, kMustNotAlias);
1512    genRegImmCheck(cUnit, kMipsCondNe, rTemp, 0, mir->offset, NULL);
1513}
1514
1515/*
1516 * The following are the first-level codegen routines that analyze the format
1517 * of each bytecode then either dispatch special purpose codegen routines
1518 * or produce corresponding Thumb instructions directly.
1519 */
1520
1521static bool handleFmt10t_Fmt20t_Fmt30t(CompilationUnit *cUnit, MIR *mir,
1522                                       BasicBlock *bb, MipsLIR *labelList)
1523{
1524    /* backward branch? */
1525    bool backwardBranch = (bb->taken->startOffset <= mir->offset);
1526
1527    if (backwardBranch &&
1528        (gDvmJit.genSuspendPoll || cUnit->jitMode == kJitLoop)) {
1529        genSuspendPoll(cUnit, mir);
1530    }
1531
1532    int numPredecessors = dvmCountSetBits(bb->taken->predecessors);
1533    /*
1534     * Things could be hoisted out of the taken block into the predecessor, so
1535     * make sure it is dominated by the predecessor.
1536     */
1537    if (numPredecessors == 1 && bb->taken->visited == false &&
1538        bb->taken->blockType == kDalvikByteCode) {
1539        cUnit->nextCodegenBlock = bb->taken;
1540    } else {
1541        /* For OP_GOTO, OP_GOTO_16, and OP_GOTO_32 */
1542        genUnconditionalBranch(cUnit, &labelList[bb->taken->id]);
1543    }
1544    return false;
1545}
1546
1547static bool handleFmt10x(CompilationUnit *cUnit, MIR *mir)
1548{
1549    Opcode dalvikOpcode = mir->dalvikInsn.opcode;
1550    if ((dalvikOpcode >= OP_UNUSED_3E) && (dalvikOpcode <= OP_UNUSED_43)) {
1551        LOGE("Codegen: got unused opcode %#x",dalvikOpcode);
1552        return true;
1553    }
1554    switch (dalvikOpcode) {
1555        case OP_RETURN_VOID_BARRIER:
1556            dvmCompilerGenMemBarrier(cUnit, 0);
1557            // Intentional fallthrough
1558        case OP_RETURN_VOID:
1559            genReturnCommon(cUnit,mir);
1560            break;
1561        case OP_UNUSED_73:
1562        case OP_UNUSED_79:
1563        case OP_UNUSED_7A:
1564            LOGE("Codegen: got unused opcode %#x",dalvikOpcode);
1565            return true;
1566        case OP_NOP:
1567            break;
1568        default:
1569            return true;
1570    }
1571    return false;
1572}
1573
1574static bool handleFmt11n_Fmt31i(CompilationUnit *cUnit, MIR *mir)
1575{
1576    RegLocation rlDest;
1577    RegLocation rlResult;
1578    if (mir->ssaRep->numDefs == 2) {
1579        rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
1580    } else {
1581        rlDest = dvmCompilerGetDest(cUnit, mir, 0);
1582    }
1583
1584    switch (mir->dalvikInsn.opcode) {
1585        case OP_CONST:
1586        case OP_CONST_4: {
1587            rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true);
1588            loadConstantNoClobber(cUnit, rlResult.lowReg, mir->dalvikInsn.vB);
1589            storeValue(cUnit, rlDest, rlResult);
1590            break;
1591        }
1592        case OP_CONST_WIDE_32: {
1593            //TUNING: single routine to load constant pair for support doubles
1594            //TUNING: load 0/-1 separately to avoid load dependency
1595            rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
1596            loadConstantNoClobber(cUnit, rlResult.lowReg, mir->dalvikInsn.vB);
1597            opRegRegImm(cUnit, kOpAsr, rlResult.highReg,
1598                        rlResult.lowReg, 31);
1599            storeValueWide(cUnit, rlDest, rlResult);
1600            break;
1601        }
1602        default:
1603            return true;
1604    }
1605    return false;
1606}
1607
1608static bool handleFmt21h(CompilationUnit *cUnit, MIR *mir)
1609{
1610    RegLocation rlDest;
1611    RegLocation rlResult;
1612    if (mir->ssaRep->numDefs == 2) {
1613        rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
1614    } else {
1615        rlDest = dvmCompilerGetDest(cUnit, mir, 0);
1616    }
1617    rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true);
1618
1619    switch (mir->dalvikInsn.opcode) {
1620        case OP_CONST_HIGH16: {
1621            loadConstantNoClobber(cUnit, rlResult.lowReg,
1622                                  mir->dalvikInsn.vB << 16);
1623            storeValue(cUnit, rlDest, rlResult);
1624            break;
1625        }
1626        case OP_CONST_WIDE_HIGH16: {
1627            loadConstantValueWide(cUnit, rlResult.lowReg, rlResult.highReg,
1628                                  0, mir->dalvikInsn.vB << 16);
1629            storeValueWide(cUnit, rlDest, rlResult);
1630            break;
1631        }
1632        default:
1633            return true;
1634    }
1635    return false;
1636}
1637
1638static bool handleFmt20bc_Fmt40sc(CompilationUnit *cUnit, MIR *mir)
1639{
1640    /* For OP_THROW_VERIFICATION_ERROR & OP_THROW_VERIFICATION_ERROR_JUMBO */
1641    genInterpSingleStep(cUnit, mir);
1642    return false;
1643}
1644
1645static bool handleFmt21c_Fmt31c_Fmt41c(CompilationUnit *cUnit, MIR *mir)
1646{
1647    RegLocation rlResult;
1648    RegLocation rlDest;
1649    RegLocation rlSrc;
1650
1651    switch (mir->dalvikInsn.opcode) {
1652        case OP_CONST_STRING_JUMBO:
1653        case OP_CONST_STRING: {
1654            void *strPtr = (void*)
1655              (cUnit->method->clazz->pDvmDex->pResStrings[mir->dalvikInsn.vB]);
1656
1657            if (strPtr == NULL) {
1658                BAIL_LOOP_COMPILATION();
1659                LOGE("Unexpected null string");
1660                dvmAbort();
1661            }
1662
1663            rlDest = dvmCompilerGetDest(cUnit, mir, 0);
1664            rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
1665            loadConstantNoClobber(cUnit, rlResult.lowReg, (int) strPtr );
1666            storeValue(cUnit, rlDest, rlResult);
1667            break;
1668        }
1669        case OP_CONST_CLASS:
1670        case OP_CONST_CLASS_JUMBO: {
1671            void *classPtr = (void*)
1672              (cUnit->method->clazz->pDvmDex->pResClasses[mir->dalvikInsn.vB]);
1673
1674            if (classPtr == NULL) {
1675                BAIL_LOOP_COMPILATION();
1676                LOGE("Unexpected null class");
1677                dvmAbort();
1678            }
1679
1680            rlDest = dvmCompilerGetDest(cUnit, mir, 0);
1681            rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
1682            loadConstantNoClobber(cUnit, rlResult.lowReg, (int) classPtr );
1683            storeValue(cUnit, rlDest, rlResult);
1684            break;
1685        }
1686        case OP_SGET:
1687        case OP_SGET_VOLATILE:
1688        case OP_SGET_VOLATILE_JUMBO:
1689        case OP_SGET_JUMBO:
1690        case OP_SGET_OBJECT:
1691        case OP_SGET_OBJECT_VOLATILE:
1692        case OP_SGET_OBJECT_VOLATILE_JUMBO:
1693        case OP_SGET_OBJECT_JUMBO:
1694        case OP_SGET_BOOLEAN:
1695        case OP_SGET_BOOLEAN_JUMBO:
1696        case OP_SGET_CHAR:
1697        case OP_SGET_CHAR_JUMBO:
1698        case OP_SGET_BYTE:
1699        case OP_SGET_BYTE_JUMBO:
1700        case OP_SGET_SHORT:
1701        case OP_SGET_SHORT_JUMBO: {
1702            int valOffset = OFFSETOF_MEMBER(StaticField, value);
1703            int tReg = dvmCompilerAllocTemp(cUnit);
1704            bool isVolatile;
1705            const Method *method = (mir->OptimizationFlags & MIR_CALLEE) ?
1706                mir->meta.calleeMethod : cUnit->method;
1707            void *fieldPtr = (void*)
1708              (method->clazz->pDvmDex->pResFields[mir->dalvikInsn.vB]);
1709
1710            if (fieldPtr == NULL) {
1711                BAIL_LOOP_COMPILATION();
1712                LOGE("Unexpected null static field");
1713                dvmAbort();
1714            }
1715
1716            /*
1717             * On SMP systems, Dalvik opcodes found to be referencing
1718             * volatile fields are rewritten to their _VOLATILE variant.
1719             * However, this does not happen on non-SMP systems. The JIT
1720             * still needs to know about volatility to avoid unsafe
1721             * optimizations so we determine volatility based on either
1722             * the opcode or the field access flags.
1723             */
1724#if ANDROID_SMP != 0
1725            Opcode opcode = mir->dalvikInsn.opcode;
1726            isVolatile = (opcode == OP_SGET_VOLATILE) ||
1727                         (opcode == OP_SGET_VOLATILE_JUMBO) ||
1728                         (opcode == OP_SGET_OBJECT_VOLATILE) ||
1729                         (opcode == OP_SGET_OBJECT_VOLATILE_JUMBO);
1730            assert(isVolatile == dvmIsVolatileField((Field *) fieldPtr));
1731#else
1732            isVolatile = dvmIsVolatileField((Field *) fieldPtr);
1733#endif
1734
1735            rlDest = dvmCompilerGetDest(cUnit, mir, 0);
1736            rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true);
1737            loadConstant(cUnit, tReg,  (int) fieldPtr + valOffset);
1738
1739            if (isVolatile) {
1740                dvmCompilerGenMemBarrier(cUnit, 0);
1741            }
1742            HEAP_ACCESS_SHADOW(true);
1743            loadWordDisp(cUnit, tReg, 0, rlResult.lowReg);
1744            HEAP_ACCESS_SHADOW(false);
1745
1746            storeValue(cUnit, rlDest, rlResult);
1747            break;
1748        }
1749        case OP_SGET_WIDE:
1750        case OP_SGET_WIDE_JUMBO: {
1751            int valOffset = OFFSETOF_MEMBER(StaticField, value);
1752            const Method *method = (mir->OptimizationFlags & MIR_CALLEE) ?
1753                mir->meta.calleeMethod : cUnit->method;
1754            void *fieldPtr = (void*)
1755              (method->clazz->pDvmDex->pResFields[mir->dalvikInsn.vB]);
1756
1757            if (fieldPtr == NULL) {
1758                BAIL_LOOP_COMPILATION();
1759                LOGE("Unexpected null static field");
1760                dvmAbort();
1761            }
1762
1763            int tReg = dvmCompilerAllocTemp(cUnit);
1764            rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
1765            rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true);
1766            loadConstant(cUnit, tReg,  (int) fieldPtr + valOffset);
1767
1768            HEAP_ACCESS_SHADOW(true);
1769            loadPair(cUnit, tReg, rlResult.lowReg, rlResult.highReg);
1770            HEAP_ACCESS_SHADOW(false);
1771
1772            storeValueWide(cUnit, rlDest, rlResult);
1773            break;
1774        }
1775        case OP_SPUT:
1776        case OP_SPUT_VOLATILE:
1777        case OP_SPUT_VOLATILE_JUMBO:
1778        case OP_SPUT_JUMBO:
1779        case OP_SPUT_OBJECT:
1780        case OP_SPUT_OBJECT_VOLATILE:
1781        case OP_SPUT_OBJECT_VOLATILE_JUMBO:
1782        case OP_SPUT_OBJECT_JUMBO:
1783        case OP_SPUT_BOOLEAN:
1784        case OP_SPUT_BOOLEAN_JUMBO:
1785        case OP_SPUT_CHAR:
1786        case OP_SPUT_CHAR_JUMBO:
1787        case OP_SPUT_BYTE:
1788        case OP_SPUT_BYTE_JUMBO:
1789        case OP_SPUT_SHORT:
1790        case OP_SPUT_SHORT_JUMBO: {
1791            int valOffset = OFFSETOF_MEMBER(StaticField, value);
1792            int tReg = dvmCompilerAllocTemp(cUnit);
1793            int objHead = 0;
1794            bool isVolatile;
1795            bool isSputObject;
1796            const Method *method = (mir->OptimizationFlags & MIR_CALLEE) ?
1797                mir->meta.calleeMethod : cUnit->method;
1798            void *fieldPtr = (void*)
1799              (method->clazz->pDvmDex->pResFields[mir->dalvikInsn.vB]);
1800            Opcode opcode = mir->dalvikInsn.opcode;
1801
1802            if (fieldPtr == NULL) {
1803                BAIL_LOOP_COMPILATION();
1804                LOGE("Unexpected null static field");
1805                dvmAbort();
1806            }
1807
1808#if ANDROID_SMP != 0
1809            isVolatile = (opcode == OP_SPUT_VOLATILE) ||
1810                         (opcode == OP_SPUT_VOLATILE_JUMBO) ||
1811                         (opcode == OP_SPUT_OBJECT_VOLATILE) ||
1812                         (opcode == OP_SPUT_OBJECT_VOLATILE_JUMBO);
1813            assert(isVolatile == dvmIsVolatileField((Field *) fieldPtr));
1814#else
1815            isVolatile = dvmIsVolatileField((Field *) fieldPtr);
1816#endif
1817
1818            isSputObject = (opcode == OP_SPUT_OBJECT) ||
1819                           (opcode == OP_SPUT_OBJECT_JUMBO) ||
1820                           (opcode == OP_SPUT_OBJECT_VOLATILE) ||
1821                           (opcode == OP_SPUT_OBJECT_VOLATILE_JUMBO);
1822
1823            rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
1824            rlSrc = loadValue(cUnit, rlSrc, kAnyReg);
1825            loadConstant(cUnit, tReg,  (int) fieldPtr);
1826            if (isSputObject) {
1827                objHead = dvmCompilerAllocTemp(cUnit);
1828                loadWordDisp(cUnit, tReg, OFFSETOF_MEMBER(Field, clazz), objHead);
1829            }
1830            if (isVolatile) {
1831                dvmCompilerGenMemBarrier(cUnit, 0);
1832            }
1833            HEAP_ACCESS_SHADOW(true);
1834            storeWordDisp(cUnit, tReg, valOffset ,rlSrc.lowReg);
1835            dvmCompilerFreeTemp(cUnit, tReg);
1836            HEAP_ACCESS_SHADOW(false);
1837            if (isVolatile) {
1838                dvmCompilerGenMemBarrier(cUnit, 0);
1839            }
1840            if (isSputObject) {
1841                /* NOTE: marking card based sfield->clazz */
1842                markCard(cUnit, rlSrc.lowReg, objHead);
1843                dvmCompilerFreeTemp(cUnit, objHead);
1844            }
1845
1846            break;
1847        }
1848        case OP_SPUT_WIDE:
1849        case OP_SPUT_WIDE_JUMBO: {
1850            int tReg = dvmCompilerAllocTemp(cUnit);
1851            int valOffset = OFFSETOF_MEMBER(StaticField, value);
1852            const Method *method = (mir->OptimizationFlags & MIR_CALLEE) ?
1853                mir->meta.calleeMethod : cUnit->method;
1854            void *fieldPtr = (void*)
1855              (method->clazz->pDvmDex->pResFields[mir->dalvikInsn.vB]);
1856
1857            if (fieldPtr == NULL) {
1858                BAIL_LOOP_COMPILATION();
1859                LOGE("Unexpected null static field");
1860                dvmAbort();
1861            }
1862
1863            rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
1864            rlSrc = loadValueWide(cUnit, rlSrc, kAnyReg);
1865            loadConstant(cUnit, tReg,  (int) fieldPtr + valOffset);
1866
1867            HEAP_ACCESS_SHADOW(true);
1868            storePair(cUnit, tReg, rlSrc.lowReg, rlSrc.highReg);
1869            HEAP_ACCESS_SHADOW(false);
1870            break;
1871        }
1872        case OP_NEW_INSTANCE:
1873        case OP_NEW_INSTANCE_JUMBO: {
1874            /*
1875             * Obey the calling convention and don't mess with the register
1876             * usage.
1877             */
1878            ClassObject *classPtr = (ClassObject *)
1879              (cUnit->method->clazz->pDvmDex->pResClasses[mir->dalvikInsn.vB]);
1880
1881            if (classPtr == NULL) {
1882                BAIL_LOOP_COMPILATION();
1883                LOGE("Unexpected null class");
1884                dvmAbort();
1885            }
1886
1887            /*
1888             * If it is going to throw, it should not make to the trace to begin
1889             * with.  However, Alloc might throw, so we need to genExportPC()
1890             */
1891            assert((classPtr->accessFlags & (ACC_INTERFACE|ACC_ABSTRACT)) == 0);
1892            dvmCompilerFlushAllRegs(cUnit);   /* Everything to home location */
1893            genExportPC(cUnit, mir);
1894            LOAD_FUNC_ADDR(cUnit, r_T9, (int)dvmAllocObject);
1895            loadConstant(cUnit, r_A0, (int) classPtr);
1896            loadConstant(cUnit, r_A1, ALLOC_DONT_TRACK);
1897            opReg(cUnit, kOpBlx, r_T9);
1898            newLIR3(cUnit, kMipsLw, r_GP, STACK_OFFSET_GP, r_SP);
1899            dvmCompilerClobberCallRegs(cUnit);
1900            /* generate a branch over if allocation is successful */
1901            MipsLIR *branchOver = opCompareBranch(cUnit, kMipsBne, r_V0, r_ZERO);
1902
1903            /*
1904             * OOM exception needs to be thrown here and cannot re-execute
1905             */
1906            loadConstant(cUnit, r_A0,
1907                         (int) (cUnit->method->insns + mir->offset));
1908            genDispatchToHandler(cUnit, TEMPLATE_THROW_EXCEPTION_COMMON);
1909            /* noreturn */
1910
1911            MipsLIR *target = newLIR0(cUnit, kMipsPseudoTargetLabel);
1912            target->defMask = ENCODE_ALL;
1913            branchOver->generic.target = (LIR *) target;
1914            rlDest = dvmCompilerGetDest(cUnit, mir, 0);
1915            rlResult = dvmCompilerGetReturn(cUnit);
1916            storeValue(cUnit, rlDest, rlResult);
1917            break;
1918        }
1919        case OP_CHECK_CAST:
1920        case OP_CHECK_CAST_JUMBO: {
1921            /*
1922             * Obey the calling convention and don't mess with the register
1923             * usage.
1924             */
1925            ClassObject *classPtr =
1926              (cUnit->method->clazz->pDvmDex->pResClasses[mir->dalvikInsn.vB]);
1927            /*
1928             * Note: It is possible that classPtr is NULL at this point,
1929             * even though this instruction has been successfully interpreted.
1930             * If the previous interpretation had a null source, the
1931             * interpreter would not have bothered to resolve the clazz.
1932             * Bail out to the interpreter in this case, and log it
1933             * so that we can tell if it happens frequently.
1934             */
1935            if (classPtr == NULL) {
1936                BAIL_LOOP_COMPILATION();
1937                LOGVV("null clazz in OP_CHECK_CAST, single-stepping");
1938                genInterpSingleStep(cUnit, mir);
1939                return false;
1940            }
1941            dvmCompilerFlushAllRegs(cUnit);   /* Everything to home location */
1942            loadConstant(cUnit, r_A1, (int) classPtr );
1943            rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
1944            rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
1945            MipsLIR *branch1 = opCompareBranch(cUnit, kMipsBeqz, rlSrc.lowReg, -1);
1946            /*
1947             *  rlSrc.lowReg now contains object->clazz.  Note that
1948             *  it could have been allocated r_A0, but we're okay so long
1949             *  as we don't do anything desctructive until r_A0 is loaded
1950             *  with clazz.
1951             */
1952            /* r_A0 now contains object->clazz */
1953            loadWordDisp(cUnit, rlSrc.lowReg, offsetof(Object, clazz), r_A0);
1954            LOAD_FUNC_ADDR(cUnit, r_T9, (int)dvmInstanceofNonTrivial);
1955            MipsLIR *branch2 = opCompareBranch(cUnit, kMipsBeq, r_A0, r_A1);
1956            opReg(cUnit, kOpBlx, r_T9);
1957            newLIR3(cUnit, kMipsLw, r_GP, STACK_OFFSET_GP, r_SP);
1958            dvmCompilerClobberCallRegs(cUnit);
1959            /*
1960             * If null, check cast failed - punt to the interpreter.  Because
1961             * interpreter will be the one throwing, we don't need to
1962             * genExportPC() here.
1963             */
1964            genRegCopy(cUnit, r_A0, r_V0);
1965            genZeroCheck(cUnit, r_V0, mir->offset, NULL);
1966            /* check cast passed - branch target here */
1967            MipsLIR *target = newLIR0(cUnit, kMipsPseudoTargetLabel);
1968            target->defMask = ENCODE_ALL;
1969            branch1->generic.target = (LIR *)target;
1970            branch2->generic.target = (LIR *)target;
1971            break;
1972        }
1973        case OP_SGET_WIDE_VOLATILE:
1974        case OP_SGET_WIDE_VOLATILE_JUMBO:
1975        case OP_SPUT_WIDE_VOLATILE:
1976        case OP_SPUT_WIDE_VOLATILE_JUMBO:
1977            genInterpSingleStep(cUnit, mir);
1978            break;
1979        default:
1980            return true;
1981    }
1982    return false;
1983}
1984
1985static bool handleFmt11x(CompilationUnit *cUnit, MIR *mir)
1986{
1987    Opcode dalvikOpcode = mir->dalvikInsn.opcode;
1988    RegLocation rlResult;
1989    switch (dalvikOpcode) {
1990        case OP_MOVE_EXCEPTION: {
1991            int exOffset = offsetof(Thread, exception);
1992            int resetReg = dvmCompilerAllocTemp(cUnit);
1993            RegLocation rlDest = dvmCompilerGetDest(cUnit, mir, 0);
1994            rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
1995            loadWordDisp(cUnit, rSELF, exOffset, rlResult.lowReg);
1996            loadConstant(cUnit, resetReg, 0);
1997            storeWordDisp(cUnit, rSELF, exOffset, resetReg);
1998            storeValue(cUnit, rlDest, rlResult);
1999           break;
2000        }
2001        case OP_MOVE_RESULT:
2002        case OP_MOVE_RESULT_OBJECT: {
2003            /* An inlined move result is effectively no-op */
2004            if (mir->OptimizationFlags & MIR_INLINED)
2005                break;
2006            RegLocation rlDest = dvmCompilerGetDest(cUnit, mir, 0);
2007            RegLocation rlSrc = LOC_DALVIK_RETURN_VAL;
2008            rlSrc.fp = rlDest.fp;
2009            storeValue(cUnit, rlDest, rlSrc);
2010            break;
2011        }
2012        case OP_MOVE_RESULT_WIDE: {
2013            /* An inlined move result is effectively no-op */
2014            if (mir->OptimizationFlags & MIR_INLINED)
2015                break;
2016            RegLocation rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
2017            RegLocation rlSrc = LOC_DALVIK_RETURN_VAL_WIDE;
2018            rlSrc.fp = rlDest.fp;
2019            storeValueWide(cUnit, rlDest, rlSrc);
2020            break;
2021        }
2022        case OP_RETURN_WIDE: {
2023            RegLocation rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
2024            RegLocation rlDest = LOC_DALVIK_RETURN_VAL_WIDE;
2025            rlDest.fp = rlSrc.fp;
2026            storeValueWide(cUnit, rlDest, rlSrc);
2027            genReturnCommon(cUnit,mir);
2028            break;
2029        }
2030        case OP_RETURN:
2031        case OP_RETURN_OBJECT: {
2032            RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
2033            RegLocation rlDest = LOC_DALVIK_RETURN_VAL;
2034            rlDest.fp = rlSrc.fp;
2035            storeValue(cUnit, rlDest, rlSrc);
2036            genReturnCommon(cUnit, mir);
2037            break;
2038        }
2039        case OP_MONITOR_EXIT:
2040        case OP_MONITOR_ENTER:
2041            genMonitor(cUnit, mir);
2042            break;
2043        case OP_THROW:
2044            genInterpSingleStep(cUnit, mir);
2045            break;
2046        default:
2047            return true;
2048    }
2049    return false;
2050}
2051
2052static bool handleFmt12x(CompilationUnit *cUnit, MIR *mir)
2053{
2054    Opcode opcode = mir->dalvikInsn.opcode;
2055    RegLocation rlDest;
2056    RegLocation rlSrc;
2057    RegLocation rlResult;
2058
2059    if ( (opcode >= OP_ADD_INT_2ADDR) && (opcode <= OP_REM_DOUBLE_2ADDR)) {
2060        return genArithOp( cUnit, mir );
2061    }
2062
2063    if (mir->ssaRep->numUses == 2)
2064        rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
2065    else
2066        rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
2067    if (mir->ssaRep->numDefs == 2)
2068        rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
2069    else
2070        rlDest = dvmCompilerGetDest(cUnit, mir, 0);
2071
2072    switch (opcode) {
2073        case OP_DOUBLE_TO_INT:
2074        case OP_INT_TO_FLOAT:
2075        case OP_FLOAT_TO_INT:
2076        case OP_DOUBLE_TO_FLOAT:
2077        case OP_FLOAT_TO_DOUBLE:
2078        case OP_INT_TO_DOUBLE:
2079        case OP_FLOAT_TO_LONG:
2080        case OP_LONG_TO_FLOAT:
2081        case OP_DOUBLE_TO_LONG:
2082        case OP_LONG_TO_DOUBLE:
2083            return genConversion(cUnit, mir);
2084        case OP_NEG_INT:
2085        case OP_NOT_INT:
2086            return genArithOpInt(cUnit, mir, rlDest, rlSrc, rlSrc);
2087        case OP_NEG_LONG:
2088        case OP_NOT_LONG:
2089            return genArithOpLong(cUnit, mir, rlDest, rlSrc, rlSrc);
2090        case OP_NEG_FLOAT:
2091            return genArithOpFloat(cUnit, mir, rlDest, rlSrc, rlSrc);
2092        case OP_NEG_DOUBLE:
2093            return genArithOpDouble(cUnit, mir, rlDest, rlSrc, rlSrc);
2094        case OP_MOVE_WIDE:
2095            storeValueWide(cUnit, rlDest, rlSrc);
2096            break;
2097        case OP_INT_TO_LONG:
2098            rlSrc = dvmCompilerUpdateLoc(cUnit, rlSrc);
2099            rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
2100            //TUNING: shouldn't loadValueDirect already check for phys reg?
2101            if (rlSrc.location == kLocPhysReg) {
2102                genRegCopy(cUnit, rlResult.lowReg, rlSrc.lowReg);
2103            } else {
2104                loadValueDirect(cUnit, rlSrc, rlResult.lowReg);
2105            }
2106            opRegRegImm(cUnit, kOpAsr, rlResult.highReg,
2107                        rlResult.lowReg, 31);
2108            storeValueWide(cUnit, rlDest, rlResult);
2109            break;
2110        case OP_LONG_TO_INT:
2111            rlSrc = dvmCompilerUpdateLocWide(cUnit, rlSrc);
2112            rlSrc = dvmCompilerWideToNarrow(cUnit, rlSrc);
2113            // Intentional fallthrough
2114        case OP_MOVE:
2115        case OP_MOVE_OBJECT:
2116            storeValue(cUnit, rlDest, rlSrc);
2117            break;
2118        case OP_INT_TO_BYTE:
2119            rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
2120            rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
2121            opRegReg(cUnit, kOp2Byte, rlResult.lowReg, rlSrc.lowReg);
2122            storeValue(cUnit, rlDest, rlResult);
2123            break;
2124        case OP_INT_TO_SHORT:
2125            rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
2126            rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
2127            opRegReg(cUnit, kOp2Short, rlResult.lowReg, rlSrc.lowReg);
2128            storeValue(cUnit, rlDest, rlResult);
2129            break;
2130        case OP_INT_TO_CHAR:
2131            rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
2132            rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
2133            opRegReg(cUnit, kOp2Char, rlResult.lowReg, rlSrc.lowReg);
2134            storeValue(cUnit, rlDest, rlResult);
2135            break;
2136        case OP_ARRAY_LENGTH: {
2137            int lenOffset = OFFSETOF_MEMBER(ArrayObject, length);
2138            rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
2139            genNullCheck(cUnit, rlSrc.sRegLow, rlSrc.lowReg,
2140                         mir->offset, NULL);
2141            rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
2142            loadWordDisp(cUnit, rlSrc.lowReg, lenOffset,
2143                         rlResult.lowReg);
2144            storeValue(cUnit, rlDest, rlResult);
2145            break;
2146        }
2147        default:
2148            return true;
2149    }
2150    return false;
2151}
2152
2153static bool handleFmt21s(CompilationUnit *cUnit, MIR *mir)
2154{
2155    Opcode dalvikOpcode = mir->dalvikInsn.opcode;
2156    RegLocation rlDest;
2157    RegLocation rlResult;
2158    int BBBB = mir->dalvikInsn.vB;
2159    if (dalvikOpcode == OP_CONST_WIDE_16) {
2160        rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
2161        rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
2162        loadConstantNoClobber(cUnit, rlResult.lowReg, BBBB);
2163        //TUNING: do high separately to avoid load dependency
2164        opRegRegImm(cUnit, kOpAsr, rlResult.highReg, rlResult.lowReg, 31);
2165        storeValueWide(cUnit, rlDest, rlResult);
2166    } else if (dalvikOpcode == OP_CONST_16) {
2167        rlDest = dvmCompilerGetDest(cUnit, mir, 0);
2168        rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true);
2169        loadConstantNoClobber(cUnit, rlResult.lowReg, BBBB);
2170        storeValue(cUnit, rlDest, rlResult);
2171    } else
2172        return true;
2173    return false;
2174}
2175
2176/* Compare agaist zero */
2177static bool handleFmt21t(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb,
2178                         MipsLIR *labelList)
2179{
2180    Opcode dalvikOpcode = mir->dalvikInsn.opcode;
2181    MipsOpCode opc = kMipsNop;
2182    int rt = -1;
2183    /* backward branch? */
2184    bool backwardBranch = (bb->taken->startOffset <= mir->offset);
2185
2186    if (backwardBranch &&
2187        (gDvmJit.genSuspendPoll || cUnit->jitMode == kJitLoop)) {
2188        genSuspendPoll(cUnit, mir);
2189    }
2190
2191    RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
2192    rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
2193
2194    switch (dalvikOpcode) {
2195        case OP_IF_EQZ:
2196            opc = kMipsBeqz;
2197            break;
2198        case OP_IF_NEZ:
2199            opc = kMipsBne;
2200            rt = r_ZERO;
2201            break;
2202        case OP_IF_LTZ:
2203            opc = kMipsBltz;
2204            break;
2205        case OP_IF_GEZ:
2206            opc = kMipsBgez;
2207            break;
2208        case OP_IF_GTZ:
2209            opc = kMipsBgtz;
2210            break;
2211        case OP_IF_LEZ:
2212            opc = kMipsBlez;
2213            break;
2214        default:
2215            LOGE("Unexpected opcode (%d) for Fmt21t", dalvikOpcode);
2216            dvmCompilerAbort(cUnit);
2217    }
2218    genConditionalBranchMips(cUnit, opc, rlSrc.lowReg, rt, &labelList[bb->taken->id]);
2219    /* This mostly likely will be optimized away in a later phase */
2220    genUnconditionalBranch(cUnit, &labelList[bb->fallThrough->id]);
2221    return false;
2222}
2223
2224static bool isPowerOfTwo(int x)
2225{
2226    return (x & (x - 1)) == 0;
2227}
2228
2229// Returns true if no more than two bits are set in 'x'.
2230static bool isPopCountLE2(unsigned int x)
2231{
2232    x &= x - 1;
2233    return (x & (x - 1)) == 0;
2234}
2235
2236// Returns the index of the lowest set bit in 'x'.
2237static int lowestSetBit(unsigned int x) {
2238    int bit_posn = 0;
2239    while ((x & 0xf) == 0) {
2240        bit_posn += 4;
2241        x >>= 4;
2242    }
2243    while ((x & 1) == 0) {
2244        bit_posn++;
2245        x >>= 1;
2246    }
2247    return bit_posn;
2248}
2249
2250// Returns true if it added instructions to 'cUnit' to divide 'rlSrc' by 'lit'
2251// and store the result in 'rlDest'.
2252static bool handleEasyDivide(CompilationUnit *cUnit, Opcode dalvikOpcode,
2253                             RegLocation rlSrc, RegLocation rlDest, int lit)
2254{
2255    if (lit < 2 || !isPowerOfTwo(lit)) {
2256        return false;
2257    }
2258    int k = lowestSetBit(lit);
2259    if (k >= 30) {
2260        // Avoid special cases.
2261        return false;
2262    }
2263    bool div = (dalvikOpcode == OP_DIV_INT_LIT8 || dalvikOpcode == OP_DIV_INT_LIT16);
2264    rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
2265    RegLocation rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
2266    if (div) {
2267        int tReg = dvmCompilerAllocTemp(cUnit);
2268        if (lit == 2) {
2269            // Division by 2 is by far the most common division by constant.
2270            opRegRegImm(cUnit, kOpLsr, tReg, rlSrc.lowReg, 32 - k);
2271            opRegRegReg(cUnit, kOpAdd, tReg, tReg, rlSrc.lowReg);
2272            opRegRegImm(cUnit, kOpAsr, rlResult.lowReg, tReg, k);
2273        } else {
2274            opRegRegImm(cUnit, kOpAsr, tReg, rlSrc.lowReg, 31);
2275            opRegRegImm(cUnit, kOpLsr, tReg, tReg, 32 - k);
2276            opRegRegReg(cUnit, kOpAdd, tReg, tReg, rlSrc.lowReg);
2277            opRegRegImm(cUnit, kOpAsr, rlResult.lowReg, tReg, k);
2278        }
2279    } else {
2280        int cReg = dvmCompilerAllocTemp(cUnit);
2281        loadConstant(cUnit, cReg, lit - 1);
2282        int tReg1 = dvmCompilerAllocTemp(cUnit);
2283        int tReg2 = dvmCompilerAllocTemp(cUnit);
2284        if (lit == 2) {
2285            opRegRegImm(cUnit, kOpLsr, tReg1, rlSrc.lowReg, 32 - k);
2286            opRegRegReg(cUnit, kOpAdd, tReg2, tReg1, rlSrc.lowReg);
2287            opRegRegReg(cUnit, kOpAnd, tReg2, tReg2, cReg);
2288            opRegRegReg(cUnit, kOpSub, rlResult.lowReg, tReg2, tReg1);
2289        } else {
2290            opRegRegImm(cUnit, kOpAsr, tReg1, rlSrc.lowReg, 31);
2291            opRegRegImm(cUnit, kOpLsr, tReg1, tReg1, 32 - k);
2292            opRegRegReg(cUnit, kOpAdd, tReg2, tReg1, rlSrc.lowReg);
2293            opRegRegReg(cUnit, kOpAnd, tReg2, tReg2, cReg);
2294            opRegRegReg(cUnit, kOpSub, rlResult.lowReg, tReg2, tReg1);
2295        }
2296    }
2297    storeValue(cUnit, rlDest, rlResult);
2298    return true;
2299}
2300
2301// Returns true if it added instructions to 'cUnit' to multiply 'rlSrc' by 'lit'
2302// and store the result in 'rlDest'.
2303static bool handleEasyMultiply(CompilationUnit *cUnit,
2304                               RegLocation rlSrc, RegLocation rlDest, int lit)
2305{
2306    // Can we simplify this multiplication?
2307    bool powerOfTwo = false;
2308    bool popCountLE2 = false;
2309    bool powerOfTwoMinusOne = false;
2310    if (lit < 2) {
2311        // Avoid special cases.
2312        return false;
2313    } else if (isPowerOfTwo(lit)) {
2314        powerOfTwo = true;
2315    } else if (isPopCountLE2(lit)) {
2316        popCountLE2 = true;
2317    } else if (isPowerOfTwo(lit + 1)) {
2318        powerOfTwoMinusOne = true;
2319    } else {
2320        return false;
2321    }
2322    rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
2323    RegLocation rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
2324    if (powerOfTwo) {
2325        // Shift.
2326        opRegRegImm(cUnit, kOpLsl, rlResult.lowReg, rlSrc.lowReg,
2327                    lowestSetBit(lit));
2328    } else if (popCountLE2) {
2329        // Shift and add and shift.
2330        int firstBit = lowestSetBit(lit);
2331        int secondBit = lowestSetBit(lit ^ (1 << firstBit));
2332        genMultiplyByTwoBitMultiplier(cUnit, rlSrc, rlResult, lit,
2333                                      firstBit, secondBit);
2334    } else {
2335        // Reverse subtract: (src << (shift + 1)) - src.
2336        assert(powerOfTwoMinusOne);
2337        // TODO: rsb dst, src, src lsl#lowestSetBit(lit + 1)
2338        int tReg = dvmCompilerAllocTemp(cUnit);
2339        opRegRegImm(cUnit, kOpLsl, tReg, rlSrc.lowReg, lowestSetBit(lit + 1));
2340        opRegRegReg(cUnit, kOpSub, rlResult.lowReg, tReg, rlSrc.lowReg);
2341    }
2342    storeValue(cUnit, rlDest, rlResult);
2343    return true;
2344}
2345
2346static bool handleFmt22b_Fmt22s(CompilationUnit *cUnit, MIR *mir)
2347{
2348    Opcode dalvikOpcode = mir->dalvikInsn.opcode;
2349    RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
2350    RegLocation rlDest = dvmCompilerGetDest(cUnit, mir, 0);
2351    RegLocation rlResult;
2352    int lit = mir->dalvikInsn.vC;
2353    OpKind op = (OpKind)0;      /* Make gcc happy */
2354    int shiftOp = false;
2355
2356    switch (dalvikOpcode) {
2357        case OP_RSUB_INT_LIT8:
2358        case OP_RSUB_INT: {
2359            int tReg;
2360            //TUNING: add support for use of Arm rsub op
2361            rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
2362            tReg = dvmCompilerAllocTemp(cUnit);
2363            loadConstant(cUnit, tReg, lit);
2364            rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
2365            opRegRegReg(cUnit, kOpSub, rlResult.lowReg,
2366                        tReg, rlSrc.lowReg);
2367            storeValue(cUnit, rlDest, rlResult);
2368            return false;
2369            break;
2370        }
2371
2372        case OP_ADD_INT_LIT8:
2373        case OP_ADD_INT_LIT16:
2374            op = kOpAdd;
2375            break;
2376        case OP_MUL_INT_LIT8:
2377        case OP_MUL_INT_LIT16: {
2378            if (handleEasyMultiply(cUnit, rlSrc, rlDest, lit)) {
2379                return false;
2380            }
2381            op = kOpMul;
2382            break;
2383        }
2384        case OP_AND_INT_LIT8:
2385        case OP_AND_INT_LIT16:
2386            op = kOpAnd;
2387            break;
2388        case OP_OR_INT_LIT8:
2389        case OP_OR_INT_LIT16:
2390            op = kOpOr;
2391            break;
2392        case OP_XOR_INT_LIT8:
2393        case OP_XOR_INT_LIT16:
2394            op = kOpXor;
2395            break;
2396        case OP_SHL_INT_LIT8:
2397            lit &= 31;
2398            shiftOp = true;
2399            op = kOpLsl;
2400            break;
2401        case OP_SHR_INT_LIT8:
2402            lit &= 31;
2403            shiftOp = true;
2404            op = kOpAsr;
2405            break;
2406        case OP_USHR_INT_LIT8:
2407            lit &= 31;
2408            shiftOp = true;
2409            op = kOpLsr;
2410            break;
2411
2412        case OP_DIV_INT_LIT8:
2413        case OP_DIV_INT_LIT16:
2414        case OP_REM_INT_LIT8:
2415        case OP_REM_INT_LIT16: {
2416            if (lit == 0) {
2417                /* Let the interpreter deal with div by 0 */
2418                genInterpSingleStep(cUnit, mir);
2419                return false;
2420            }
2421            if (handleEasyDivide(cUnit, dalvikOpcode, rlSrc, rlDest, lit)) {
2422                return false;
2423            }
2424
2425            MipsOpCode opc;
2426            int divReg;
2427
2428            if ((dalvikOpcode == OP_DIV_INT_LIT8) ||
2429                (dalvikOpcode == OP_DIV_INT_LIT16)) {
2430                opc = kMipsMflo;
2431                divReg = r_LO;
2432            } else {
2433                opc = kMipsMfhi;
2434                divReg = r_HI;
2435            }
2436
2437            rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
2438            int tReg = dvmCompilerAllocTemp(cUnit);
2439            newLIR3(cUnit, kMipsAddiu, tReg, r_ZERO, lit);
2440            newLIR4(cUnit, kMipsDiv, r_HI, r_LO, rlSrc.lowReg, tReg);
2441            rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
2442            newLIR2(cUnit, opc, rlResult.lowReg, divReg);
2443            dvmCompilerFreeTemp(cUnit, tReg);
2444            storeValue(cUnit, rlDest, rlResult);
2445            return false;
2446            break;
2447        }
2448        default:
2449            return true;
2450    }
2451    rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
2452    rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
2453    // Avoid shifts by literal 0 - no support in Thumb.  Change to copy
2454    if (shiftOp && (lit == 0)) {
2455        genRegCopy(cUnit, rlResult.lowReg, rlSrc.lowReg);
2456    } else {
2457        opRegRegImm(cUnit, op, rlResult.lowReg, rlSrc.lowReg, lit);
2458    }
2459    storeValue(cUnit, rlDest, rlResult);
2460    return false;
2461}
2462
2463static bool handleFmt22c_Fmt52c(CompilationUnit *cUnit, MIR *mir)
2464{
2465    Opcode dalvikOpcode = mir->dalvikInsn.opcode;
2466    int fieldOffset = -1;
2467    bool isVolatile = false;
2468    switch (dalvikOpcode) {
2469        /*
2470         * Wide volatiles currently handled via single step.
2471         * Add them here if generating in-line code.
2472         *     case OP_IGET_WIDE_VOLATILE:
2473         *     case OP_IGET_WIDE_VOLATILE_JUMBO:
2474         *     case OP_IPUT_WIDE_VOLATILE:
2475         *     case OP_IPUT_WIDE_VOLATILE_JUMBO:
2476         */
2477        case OP_IGET_VOLATILE:
2478        case OP_IGET_VOLATILE_JUMBO:
2479        case OP_IGET_OBJECT_VOLATILE:
2480        case OP_IGET_OBJECT_VOLATILE_JUMBO:
2481        case OP_IPUT_VOLATILE:
2482        case OP_IPUT_VOLATILE_JUMBO:
2483        case OP_IPUT_OBJECT_VOLATILE:
2484        case OP_IPUT_OBJECT_VOLATILE_JUMBO:
2485#if ANDROID_SMP != 0
2486            isVolatile = true;
2487        // NOTE: intentional fallthrough
2488#endif
2489        case OP_IGET:
2490        case OP_IGET_JUMBO:
2491        case OP_IGET_WIDE:
2492        case OP_IGET_WIDE_JUMBO:
2493        case OP_IGET_OBJECT:
2494        case OP_IGET_OBJECT_JUMBO:
2495        case OP_IGET_BOOLEAN:
2496        case OP_IGET_BOOLEAN_JUMBO:
2497        case OP_IGET_BYTE:
2498        case OP_IGET_BYTE_JUMBO:
2499        case OP_IGET_CHAR:
2500        case OP_IGET_CHAR_JUMBO:
2501        case OP_IGET_SHORT:
2502        case OP_IGET_SHORT_JUMBO:
2503        case OP_IPUT:
2504        case OP_IPUT_JUMBO:
2505        case OP_IPUT_WIDE:
2506        case OP_IPUT_WIDE_JUMBO:
2507        case OP_IPUT_OBJECT:
2508        case OP_IPUT_OBJECT_JUMBO:
2509        case OP_IPUT_BOOLEAN:
2510        case OP_IPUT_BOOLEAN_JUMBO:
2511        case OP_IPUT_BYTE:
2512        case OP_IPUT_BYTE_JUMBO:
2513        case OP_IPUT_CHAR:
2514        case OP_IPUT_CHAR_JUMBO:
2515        case OP_IPUT_SHORT:
2516        case OP_IPUT_SHORT_JUMBO: {
2517            const Method *method = (mir->OptimizationFlags & MIR_CALLEE) ?
2518                mir->meta.calleeMethod : cUnit->method;
2519            Field *fieldPtr =
2520                method->clazz->pDvmDex->pResFields[mir->dalvikInsn.vC];
2521
2522            if (fieldPtr == NULL) {
2523                BAIL_LOOP_COMPILATION();
2524                LOGE("Unexpected null instance field");
2525                dvmAbort();
2526            }
2527#if ANDROID_SMP != 0
2528            assert(isVolatile == dvmIsVolatileField((Field *) fieldPtr));
2529#else
2530            isVolatile = dvmIsVolatileField((Field *) fieldPtr);
2531#endif
2532            fieldOffset = ((InstField *)fieldPtr)->byteOffset;
2533            break;
2534        }
2535        default:
2536            break;
2537    }
2538
2539    switch (dalvikOpcode) {
2540        case OP_NEW_ARRAY:
2541        case OP_NEW_ARRAY_JUMBO: {
2542#if 0 /* 080 triggers assert in Interp.c:1290 for out of memory exception.
2543             i think the assert is in error and should be disabled. With
2544             asserts disabled, 080 passes. */
2545genInterpSingleStep(cUnit, mir);
2546return false;
2547#endif
2548            // Generates a call - use explicit registers
2549            RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
2550            RegLocation rlDest = dvmCompilerGetDest(cUnit, mir, 0);
2551            RegLocation rlResult;
2552            void *classPtr = (void*)
2553              (cUnit->method->clazz->pDvmDex->pResClasses[mir->dalvikInsn.vC]);
2554
2555            if (classPtr == NULL) {
2556                BAIL_LOOP_COMPILATION();
2557                LOGE("Unexpected null class");
2558                dvmAbort();
2559            }
2560
2561            dvmCompilerFlushAllRegs(cUnit);   /* Everything to home location */
2562            genExportPC(cUnit, mir);
2563            loadValueDirectFixed(cUnit, rlSrc, r_A1);   /* Len */
2564            loadConstant(cUnit, r_A0, (int) classPtr );
2565            LOAD_FUNC_ADDR(cUnit, r_T9, (int)dvmAllocArrayByClass);
2566            /*
2567             * "len < 0": bail to the interpreter to re-execute the
2568             * instruction
2569             */
2570            genRegImmCheck(cUnit, kMipsCondMi, r_A1, 0, mir->offset, NULL);
2571            loadConstant(cUnit, r_A2, ALLOC_DONT_TRACK);
2572            opReg(cUnit, kOpBlx, r_T9);
2573            newLIR3(cUnit, kMipsLw, r_GP, STACK_OFFSET_GP, r_SP);
2574            dvmCompilerClobberCallRegs(cUnit);
2575            /* generate a branch over if allocation is successful */
2576            MipsLIR *branchOver = opCompareBranch(cUnit, kMipsBne, r_V0, r_ZERO);
2577            /*
2578             * OOM exception needs to be thrown here and cannot re-execute
2579             */
2580            loadConstant(cUnit, r_A0,
2581                         (int) (cUnit->method->insns + mir->offset));
2582            genDispatchToHandler(cUnit, TEMPLATE_THROW_EXCEPTION_COMMON);
2583            /* noreturn */
2584
2585            MipsLIR *target = newLIR0(cUnit, kMipsPseudoTargetLabel);
2586            target->defMask = ENCODE_ALL;
2587            branchOver->generic.target = (LIR *) target;
2588            rlResult = dvmCompilerGetReturn(cUnit);
2589            storeValue(cUnit, rlDest, rlResult);
2590            break;
2591        }
2592        case OP_INSTANCE_OF:
2593        case OP_INSTANCE_OF_JUMBO: {
2594            // May generate a call - use explicit registers
2595            RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
2596            RegLocation rlDest = dvmCompilerGetDest(cUnit, mir, 0);
2597            RegLocation rlResult;
2598            ClassObject *classPtr =
2599              (cUnit->method->clazz->pDvmDex->pResClasses[mir->dalvikInsn.vC]);
2600            /*
2601             * Note: It is possible that classPtr is NULL at this point,
2602             * even though this instruction has been successfully interpreted.
2603             * If the previous interpretation had a null source, the
2604             * interpreter would not have bothered to resolve the clazz.
2605             * Bail out to the interpreter in this case, and log it
2606             * so that we can tell if it happens frequently.
2607             */
2608            if (classPtr == NULL) {
2609                BAIL_LOOP_COMPILATION();
2610                LOGD("null clazz in OP_INSTANCE_OF, single-stepping");
2611                genInterpSingleStep(cUnit, mir);
2612                break;
2613            }
2614            dvmCompilerFlushAllRegs(cUnit);   /* Everything to home location */
2615            loadValueDirectFixed(cUnit, rlSrc, r_V0);  /* Ref */
2616            loadConstant(cUnit, r_A2, (int) classPtr );
2617            /* When taken r_V0 has NULL which can be used for store directly */
2618            MipsLIR *branch1 = opCompareBranch(cUnit, kMipsBeqz, r_V0, -1);
2619            /* r_A1 now contains object->clazz */
2620            loadWordDisp(cUnit, r_V0, offsetof(Object, clazz), r_A1);
2621            /* r_A1 now contains object->clazz */
2622            LOAD_FUNC_ADDR(cUnit, r_T9, (int)dvmInstanceofNonTrivial);
2623            loadConstant(cUnit, r_V0, 1);                /* Assume true */
2624            MipsLIR *branch2 = opCompareBranch(cUnit, kMipsBeq, r_A1, r_A2);
2625            genRegCopy(cUnit, r_A0, r_A1);
2626            genRegCopy(cUnit, r_A1, r_A2);
2627            opReg(cUnit, kOpBlx, r_T9);
2628            newLIR3(cUnit, kMipsLw, r_GP, STACK_OFFSET_GP, r_SP);
2629            dvmCompilerClobberCallRegs(cUnit);
2630            /* branch target here */
2631            MipsLIR *target = newLIR0(cUnit, kMipsPseudoTargetLabel);
2632            target->defMask = ENCODE_ALL;
2633            rlResult = dvmCompilerGetReturn(cUnit);
2634            storeValue(cUnit, rlDest, rlResult);
2635            branch1->generic.target = (LIR *)target;
2636            branch2->generic.target = (LIR *)target;
2637            break;
2638        }
2639        case OP_IGET_WIDE:
2640        case OP_IGET_WIDE_JUMBO:
2641            genIGetWide(cUnit, mir, fieldOffset);
2642            break;
2643        case OP_IGET_VOLATILE:
2644        case OP_IGET_VOLATILE_JUMBO:
2645        case OP_IGET_OBJECT_VOLATILE:
2646        case OP_IGET_OBJECT_VOLATILE_JUMBO:
2647        case OP_IGET:
2648        case OP_IGET_JUMBO:
2649        case OP_IGET_OBJECT:
2650        case OP_IGET_OBJECT_JUMBO:
2651        case OP_IGET_BOOLEAN:
2652        case OP_IGET_BOOLEAN_JUMBO:
2653        case OP_IGET_BYTE:
2654        case OP_IGET_BYTE_JUMBO:
2655        case OP_IGET_CHAR:
2656        case OP_IGET_CHAR_JUMBO:
2657        case OP_IGET_SHORT:
2658        case OP_IGET_SHORT_JUMBO:
2659            genIGet(cUnit, mir, kWord, fieldOffset, isVolatile);
2660            break;
2661        case OP_IPUT_WIDE:
2662        case OP_IPUT_WIDE_JUMBO:
2663            genIPutWide(cUnit, mir, fieldOffset);
2664            break;
2665        case OP_IPUT_VOLATILE:
2666        case OP_IPUT_VOLATILE_JUMBO:
2667        case OP_IPUT:
2668        case OP_IPUT_JUMBO:
2669        case OP_IPUT_BOOLEAN:
2670        case OP_IPUT_BOOLEAN_JUMBO:
2671        case OP_IPUT_BYTE:
2672        case OP_IPUT_BYTE_JUMBO:
2673        case OP_IPUT_CHAR:
2674        case OP_IPUT_CHAR_JUMBO:
2675        case OP_IPUT_SHORT:
2676        case OP_IPUT_SHORT_JUMBO:
2677            genIPut(cUnit, mir, kWord, fieldOffset, false, isVolatile);
2678            break;
2679        case OP_IPUT_OBJECT_VOLATILE:
2680        case OP_IPUT_OBJECT_VOLATILE_JUMBO:
2681        case OP_IPUT_OBJECT:
2682        case OP_IPUT_OBJECT_JUMBO:
2683            genIPut(cUnit, mir, kWord, fieldOffset, true, isVolatile);
2684            break;
2685        case OP_IGET_WIDE_VOLATILE:
2686        case OP_IGET_WIDE_VOLATILE_JUMBO:
2687        case OP_IPUT_WIDE_VOLATILE:
2688        case OP_IPUT_WIDE_VOLATILE_JUMBO:
2689            genInterpSingleStep(cUnit, mir);
2690            break;
2691        default:
2692            return true;
2693    }
2694    return false;
2695}
2696
2697static bool handleFmt22cs(CompilationUnit *cUnit, MIR *mir)
2698{
2699    Opcode dalvikOpcode = mir->dalvikInsn.opcode;
2700    int fieldOffset =  mir->dalvikInsn.vC;
2701    switch (dalvikOpcode) {
2702        case OP_IGET_QUICK:
2703        case OP_IGET_OBJECT_QUICK:
2704            genIGet(cUnit, mir, kWord, fieldOffset, false);
2705            break;
2706        case OP_IPUT_QUICK:
2707            genIPut(cUnit, mir, kWord, fieldOffset, false, false);
2708            break;
2709        case OP_IPUT_OBJECT_QUICK:
2710            genIPut(cUnit, mir, kWord, fieldOffset, true, false);
2711            break;
2712        case OP_IGET_WIDE_QUICK:
2713            genIGetWide(cUnit, mir, fieldOffset);
2714            break;
2715        case OP_IPUT_WIDE_QUICK:
2716            genIPutWide(cUnit, mir, fieldOffset);
2717            break;
2718        default:
2719            return true;
2720    }
2721    return false;
2722
2723}
2724
2725/* Compare against zero */
2726static bool handleFmt22t(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb,
2727                         MipsLIR *labelList)
2728{
2729    Opcode dalvikOpcode = mir->dalvikInsn.opcode;
2730    MipsConditionCode cond;
2731    MipsOpCode opc = kMipsNop;
2732    MipsLIR * test = NULL;
2733    /* backward branch? */
2734    bool backwardBranch = (bb->taken->startOffset <= mir->offset);
2735
2736    if (backwardBranch &&
2737        (gDvmJit.genSuspendPoll || cUnit->jitMode == kJitLoop)) {
2738        genSuspendPoll(cUnit, mir);
2739    }
2740
2741    RegLocation rlSrc1 = dvmCompilerGetSrc(cUnit, mir, 0);
2742    RegLocation rlSrc2 = dvmCompilerGetSrc(cUnit, mir, 1);
2743    rlSrc1 = loadValue(cUnit, rlSrc1, kCoreReg);
2744    rlSrc2 = loadValue(cUnit, rlSrc2, kCoreReg);
2745    int reg1 = rlSrc1.lowReg;
2746    int reg2 = rlSrc2.lowReg;
2747    int tReg;
2748
2749    switch (dalvikOpcode) {
2750        case OP_IF_EQ:
2751            opc = kMipsBeq;
2752            break;
2753        case OP_IF_NE:
2754            opc = kMipsBne;
2755            break;
2756        case OP_IF_LT:
2757            opc = kMipsBne;
2758            tReg = dvmCompilerAllocTemp(cUnit);
2759            test = newLIR3(cUnit, kMipsSlt, tReg, reg1, reg2);
2760            reg1 = tReg;
2761            reg2 = r_ZERO;
2762            break;
2763        case OP_IF_LE:
2764            opc = kMipsBeqz;
2765            tReg = dvmCompilerAllocTemp(cUnit);
2766            test = newLIR3(cUnit, kMipsSlt, tReg, reg2, reg1);
2767            reg1 = tReg;
2768            reg2 = -1;
2769            break;
2770        case OP_IF_GT:
2771            opc = kMipsBne;
2772            tReg = dvmCompilerAllocTemp(cUnit);
2773            test = newLIR3(cUnit, kMipsSlt, tReg, reg2, reg1);
2774            reg1 = tReg;
2775            reg2 = r_ZERO;
2776            break;
2777        case OP_IF_GE:
2778            opc = kMipsBeqz;
2779            tReg = dvmCompilerAllocTemp(cUnit);
2780            test = newLIR3(cUnit, kMipsSlt, tReg, reg1, reg2);
2781            reg1 = tReg;
2782            reg2 = -1;
2783            break;
2784        default:
2785            cond = (MipsConditionCode)0;
2786            LOGE("Unexpected opcode (%d) for Fmt22t", dalvikOpcode);
2787            dvmCompilerAbort(cUnit);
2788    }
2789
2790    genConditionalBranchMips(cUnit, opc, reg1, reg2, &labelList[bb->taken->id]);
2791    /* This mostly likely will be optimized away in a later phase */
2792    genUnconditionalBranch(cUnit, &labelList[bb->fallThrough->id]);
2793    return false;
2794}
2795
2796static bool handleFmt22x_Fmt32x(CompilationUnit *cUnit, MIR *mir)
2797{
2798    Opcode opcode = mir->dalvikInsn.opcode;
2799
2800    switch (opcode) {
2801        case OP_MOVE_16:
2802        case OP_MOVE_OBJECT_16:
2803        case OP_MOVE_FROM16:
2804        case OP_MOVE_OBJECT_FROM16: {
2805            storeValue(cUnit, dvmCompilerGetDest(cUnit, mir, 0),
2806                       dvmCompilerGetSrc(cUnit, mir, 0));
2807            break;
2808        }
2809        case OP_MOVE_WIDE_16:
2810        case OP_MOVE_WIDE_FROM16: {
2811            storeValueWide(cUnit, dvmCompilerGetDestWide(cUnit, mir, 0, 1),
2812                           dvmCompilerGetSrcWide(cUnit, mir, 0, 1));
2813            break;
2814        }
2815        default:
2816            return true;
2817    }
2818    return false;
2819}
2820
2821static bool handleFmt23x(CompilationUnit *cUnit, MIR *mir)
2822{
2823    Opcode opcode = mir->dalvikInsn.opcode;
2824    RegLocation rlSrc1;
2825    RegLocation rlSrc2;
2826    RegLocation rlDest;
2827
2828    if ((opcode >= OP_ADD_INT) && (opcode <= OP_REM_DOUBLE)) {
2829        return genArithOp( cUnit, mir );
2830    }
2831
2832    /* APUTs have 3 sources and no targets */
2833    if (mir->ssaRep->numDefs == 0) {
2834        if (mir->ssaRep->numUses == 3) {
2835            rlDest = dvmCompilerGetSrc(cUnit, mir, 0);
2836            rlSrc1 = dvmCompilerGetSrc(cUnit, mir, 1);
2837            rlSrc2 = dvmCompilerGetSrc(cUnit, mir, 2);
2838        } else {
2839            assert(mir->ssaRep->numUses == 4);
2840            rlDest = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
2841            rlSrc1 = dvmCompilerGetSrc(cUnit, mir, 2);
2842            rlSrc2 = dvmCompilerGetSrc(cUnit, mir, 3);
2843        }
2844    } else {
2845        /* Two sources and 1 dest.  Deduce the operand sizes */
2846        if (mir->ssaRep->numUses == 4) {
2847            rlSrc1 = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
2848            rlSrc2 = dvmCompilerGetSrcWide(cUnit, mir, 2, 3);
2849        } else {
2850            assert(mir->ssaRep->numUses == 2);
2851            rlSrc1 = dvmCompilerGetSrc(cUnit, mir, 0);
2852            rlSrc2 = dvmCompilerGetSrc(cUnit, mir, 1);
2853        }
2854        if (mir->ssaRep->numDefs == 2) {
2855            rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
2856        } else {
2857            assert(mir->ssaRep->numDefs == 1);
2858            rlDest = dvmCompilerGetDest(cUnit, mir, 0);
2859        }
2860    }
2861
2862    switch (opcode) {
2863        case OP_CMPL_FLOAT:
2864        case OP_CMPG_FLOAT:
2865        case OP_CMPL_DOUBLE:
2866        case OP_CMPG_DOUBLE:
2867            return genCmpFP(cUnit, mir, rlDest, rlSrc1, rlSrc2);
2868        case OP_CMP_LONG:
2869            genCmpLong(cUnit, mir, rlDest, rlSrc1, rlSrc2);
2870            break;
2871        case OP_AGET_WIDE:
2872            genArrayGet(cUnit, mir, kLong, rlSrc1, rlSrc2, rlDest, 3);
2873            break;
2874        case OP_AGET:
2875        case OP_AGET_OBJECT:
2876            genArrayGet(cUnit, mir, kWord, rlSrc1, rlSrc2, rlDest, 2);
2877            break;
2878        case OP_AGET_BOOLEAN:
2879            genArrayGet(cUnit, mir, kUnsignedByte, rlSrc1, rlSrc2, rlDest, 0);
2880            break;
2881        case OP_AGET_BYTE:
2882            genArrayGet(cUnit, mir, kSignedByte, rlSrc1, rlSrc2, rlDest, 0);
2883            break;
2884        case OP_AGET_CHAR:
2885            genArrayGet(cUnit, mir, kUnsignedHalf, rlSrc1, rlSrc2, rlDest, 1);
2886            break;
2887        case OP_AGET_SHORT:
2888            genArrayGet(cUnit, mir, kSignedHalf, rlSrc1, rlSrc2, rlDest, 1);
2889            break;
2890        case OP_APUT_WIDE:
2891            genArrayPut(cUnit, mir, kLong, rlSrc1, rlSrc2, rlDest, 3);
2892            break;
2893        case OP_APUT:
2894            genArrayPut(cUnit, mir, kWord, rlSrc1, rlSrc2, rlDest, 2);
2895            break;
2896        case OP_APUT_OBJECT:
2897            genArrayObjectPut(cUnit, mir, rlSrc1, rlSrc2, rlDest, 2);
2898            break;
2899        case OP_APUT_SHORT:
2900        case OP_APUT_CHAR:
2901            genArrayPut(cUnit, mir, kUnsignedHalf, rlSrc1, rlSrc2, rlDest, 1);
2902            break;
2903        case OP_APUT_BYTE:
2904        case OP_APUT_BOOLEAN:
2905            genArrayPut(cUnit, mir, kUnsignedByte, rlSrc1, rlSrc2, rlDest, 0);
2906            break;
2907        default:
2908            return true;
2909    }
2910    return false;
2911}
2912
2913/*
2914 * Find the matching case.
2915 *
2916 * return values:
2917 * r_RESULT0 (low 32-bit): pc of the chaining cell corresponding to the resolved case,
2918 *    including default which is placed at MIN(size, MAX_CHAINED_SWITCH_CASES).
2919 * r_RESULT1 (high 32-bit): the branch offset of the matching case (only for indexes
2920 *    above MAX_CHAINED_SWITCH_CASES).
2921 *
2922 * Instructions around the call are:
2923 *
2924 * jalr &findPackedSwitchIndex
2925 * nop
2926 * lw gp, 84(sp) |
2927 * addu          | 20 bytes for these 5 instructions
2928 * move          | (NOTE: if this sequence is shortened or lengthened, then
2929 * jr            |  the 20 byte offset added below in 3 places must be changed
2930 * nop           |  accordingly.)
2931 * chaining cell for case 0 [16 bytes]
2932 * chaining cell for case 1 [16 bytes]
2933 *               :
2934 * chaining cell for case MIN(size, MAX_CHAINED_SWITCH_CASES)-1 [16 bytes]
2935 * chaining cell for case default [16 bytes]
2936 * noChain exit
2937 */
2938static u8 findPackedSwitchIndex(const u2* switchData, int testVal)
2939{
2940    int size;
2941    int firstKey;
2942    const int *entries;
2943    int index;
2944    int jumpIndex;
2945    uintptr_t caseDPCOffset = 0;
2946
2947    /*
2948     * Packed switch data format:
2949     *  ushort ident = 0x0100   magic value
2950     *  ushort size             number of entries in the table
2951     *  int first_key           first (and lowest) switch case value
2952     *  int targets[size]       branch targets, relative to switch opcode
2953     *
2954     * Total size is (4+size*2) 16-bit code units.
2955     */
2956    size = switchData[1];
2957    assert(size > 0);
2958
2959    firstKey = switchData[2];
2960    firstKey |= switchData[3] << 16;
2961
2962
2963    /* The entries are guaranteed to be aligned on a 32-bit boundary;
2964     * we can treat them as a native int array.
2965     */
2966    entries = (const int*) &switchData[4];
2967    assert(((u4)entries & 0x3) == 0);
2968
2969    index = testVal - firstKey;
2970
2971    /* Jump to the default cell */
2972    if (index < 0 || index >= size) {
2973        jumpIndex = MIN(size, MAX_CHAINED_SWITCH_CASES);
2974    /* Jump to the non-chaining exit point */
2975    } else if (index >= MAX_CHAINED_SWITCH_CASES) {
2976        jumpIndex = MAX_CHAINED_SWITCH_CASES + 1;
2977#ifdef HAVE_LITTLE_ENDIAN
2978        caseDPCOffset = entries[index];
2979#else
2980        caseDPCOffset = (unsigned int)entries[index] >> 16 | entries[index] << 16;
2981#endif
2982    /* Jump to the inline chaining cell */
2983    } else {
2984        jumpIndex = index;
2985    }
2986
2987    return (((u8) caseDPCOffset) << 32) | (u8) (jumpIndex * CHAIN_CELL_NORMAL_SIZE + 20);
2988}
2989
2990/* See comments for findPackedSwitchIndex */
2991static u8 findSparseSwitchIndex(const u2* switchData, int testVal)
2992{
2993    int size;
2994    const int *keys;
2995    const int *entries;
2996    /* In Thumb mode pc is 4 ahead of the "mov r2, pc" instruction */
2997    int i;
2998
2999    /*
3000     * Sparse switch data format:
3001     *  ushort ident = 0x0200   magic value
3002     *  ushort size             number of entries in the table; > 0
3003     *  int keys[size]          keys, sorted low-to-high; 32-bit aligned
3004     *  int targets[size]       branch targets, relative to switch opcode
3005     *
3006     * Total size is (2+size*4) 16-bit code units.
3007     */
3008
3009    size = switchData[1];
3010    assert(size > 0);
3011
3012    /* The keys are guaranteed to be aligned on a 32-bit boundary;
3013     * we can treat them as a native int array.
3014     */
3015    keys = (const int*) &switchData[2];
3016    assert(((u4)keys & 0x3) == 0);
3017
3018    /* The entries are guaranteed to be aligned on a 32-bit boundary;
3019     * we can treat them as a native int array.
3020     */
3021    entries = keys + size;
3022    assert(((u4)entries & 0x3) == 0);
3023
3024    /*
3025     * Run through the list of keys, which are guaranteed to
3026     * be sorted low-to-high.
3027     *
3028     * Most tables have 3-4 entries.  Few have more than 10.  A binary
3029     * search here is probably not useful.
3030     */
3031    for (i = 0; i < size; i++) {
3032#ifdef HAVE_LITTLE_ENDIAN
3033        int k = keys[i];
3034        if (k == testVal) {
3035            /* MAX_CHAINED_SWITCH_CASES + 1 is the start of the overflow case */
3036            int jumpIndex = (i < MAX_CHAINED_SWITCH_CASES) ?
3037                           i : MAX_CHAINED_SWITCH_CASES + 1;
3038            return (((u8) entries[i]) << 32) | (u8) (jumpIndex * CHAIN_CELL_NORMAL_SIZE + 20);
3039#else
3040        int k = (unsigned int)keys[i] >> 16 | keys[i] << 16;
3041        if (k == testVal) {
3042            /* MAX_CHAINED_SWITCH_CASES + 1 is the start of the overflow case */
3043            int jumpIndex = (i < MAX_CHAINED_SWITCH_CASES) ?
3044                           i : MAX_CHAINED_SWITCH_CASES + 1;
3045            int temp = (unsigned int)entries[i] >> 16 | entries[i] << 16;
3046            return (((u8) temp) << 32) | (u8) (jumpIndex * CHAIN_CELL_NORMAL_SIZE + 20);
3047#endif
3048        } else if (k > testVal) {
3049            break;
3050        }
3051    }
3052    return MIN(size, MAX_CHAINED_SWITCH_CASES) * CHAIN_CELL_NORMAL_SIZE + 20;
3053}
3054
3055static bool handleFmt31t(CompilationUnit *cUnit, MIR *mir)
3056{
3057    Opcode dalvikOpcode = mir->dalvikInsn.opcode;
3058    switch (dalvikOpcode) {
3059        case OP_FILL_ARRAY_DATA: {
3060            RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
3061            // Making a call - use explicit registers
3062            dvmCompilerFlushAllRegs(cUnit);   /* Everything to home location */
3063            genExportPC(cUnit, mir);
3064            loadValueDirectFixed(cUnit, rlSrc, r_A0);
3065            LOAD_FUNC_ADDR(cUnit, r_T9, (int)dvmInterpHandleFillArrayData);
3066            loadConstant(cUnit, r_A1,
3067               (int) (cUnit->method->insns + mir->offset + mir->dalvikInsn.vB));
3068            opReg(cUnit, kOpBlx, r_T9);
3069            newLIR3(cUnit, kMipsLw, r_GP, STACK_OFFSET_GP, r_SP);
3070            dvmCompilerClobberCallRegs(cUnit);
3071            /* generate a branch over if successful */
3072            MipsLIR *branchOver = opCompareBranch(cUnit, kMipsBne, r_V0, r_ZERO);
3073            loadConstant(cUnit, r_A0,
3074                         (int) (cUnit->method->insns + mir->offset));
3075            genDispatchToHandler(cUnit, TEMPLATE_THROW_EXCEPTION_COMMON);
3076            MipsLIR *target = newLIR0(cUnit, kMipsPseudoTargetLabel);
3077            target->defMask = ENCODE_ALL;
3078            branchOver->generic.target = (LIR *) target;
3079            break;
3080        }
3081        /*
3082         * Compute the goto target of up to
3083         * MIN(switchSize, MAX_CHAINED_SWITCH_CASES) + 1 chaining cells.
3084         * See the comment before findPackedSwitchIndex for the code layout.
3085         */
3086        case OP_PACKED_SWITCH:
3087        case OP_SPARSE_SWITCH: {
3088            RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
3089            dvmCompilerFlushAllRegs(cUnit);   /* Everything to home location */
3090            loadValueDirectFixed(cUnit, rlSrc, r_A1);
3091            dvmCompilerLockAllTemps(cUnit);
3092
3093            if (dalvikOpcode == OP_PACKED_SWITCH) {
3094                LOAD_FUNC_ADDR(cUnit, r_T9, (int)findPackedSwitchIndex);
3095            } else {
3096                LOAD_FUNC_ADDR(cUnit, r_T9, (int)findSparseSwitchIndex);
3097            }
3098            /* r_A0 <- Addr of the switch data */
3099            loadConstant(cUnit, r_A0,
3100               (int) (cUnit->method->insns + mir->offset + mir->dalvikInsn.vB));
3101            opReg(cUnit, kOpBlx, r_T9);
3102            newLIR3(cUnit, kMipsLw, r_GP, STACK_OFFSET_GP, r_SP);
3103            dvmCompilerClobberCallRegs(cUnit);
3104            /* pc <- computed goto target using value in RA */
3105            newLIR3(cUnit, kMipsAddu, r_A0, r_RA, r_RESULT0);
3106            newLIR2(cUnit, kMipsMove, r_A1, r_RESULT1);
3107            newLIR1(cUnit, kMipsJr, r_A0);
3108            newLIR0(cUnit, kMipsNop); /* for maintaining 20 byte offset */
3109            break;
3110        }
3111        default:
3112            return true;
3113    }
3114    return false;
3115}
3116
3117/*
3118 * See the example of predicted inlining listed before the
3119 * genValidationForPredictedInline function. The function here takes care the
3120 * branch over at 0x4858de78 and the misprediction target at 0x4858de7a.
3121 */
3122static void genLandingPadForMispredictedCallee(CompilationUnit *cUnit, MIR *mir,
3123                                               BasicBlock *bb,
3124                                               MipsLIR *labelList)
3125{
3126    BasicBlock *fallThrough = bb->fallThrough;
3127
3128    /* Bypass the move-result block if there is one */
3129    if (fallThrough->firstMIRInsn) {
3130        assert(fallThrough->firstMIRInsn->OptimizationFlags & MIR_INLINED_PRED);
3131        fallThrough = fallThrough->fallThrough;
3132    }
3133    /* Generate a branch over if the predicted inlining is correct */
3134    genUnconditionalBranch(cUnit, &labelList[fallThrough->id]);
3135
3136    /* Reset the register state */
3137    dvmCompilerResetRegPool(cUnit);
3138    dvmCompilerClobberAllRegs(cUnit);
3139    dvmCompilerResetNullCheck(cUnit);
3140
3141    /* Target for the slow invoke path */
3142    MipsLIR *target = newLIR0(cUnit, kMipsPseudoTargetLabel);
3143    target->defMask = ENCODE_ALL;
3144    /* Hook up the target to the verification branch */
3145    mir->meta.callsiteInfo->misPredBranchOver->target = (LIR *) target;
3146}
3147
3148static bool handleFmt35c_3rc_5rc(CompilationUnit *cUnit, MIR *mir,
3149                             BasicBlock *bb, MipsLIR *labelList)
3150{
3151    MipsLIR *retChainingCell = NULL;
3152    MipsLIR *pcrLabel = NULL;
3153
3154    /* An invoke with the MIR_INLINED is effectively a no-op */
3155    if (mir->OptimizationFlags & MIR_INLINED)
3156        return false;
3157
3158    if (bb->fallThrough != NULL)
3159        retChainingCell = &labelList[bb->fallThrough->id];
3160
3161    DecodedInstruction *dInsn = &mir->dalvikInsn;
3162    switch (mir->dalvikInsn.opcode) {
3163        /*
3164         * calleeMethod = this->clazz->vtable[
3165         *     method->clazz->pDvmDex->pResMethods[BBBB]->methodIndex
3166         * ]
3167         */
3168        case OP_INVOKE_VIRTUAL:
3169        case OP_INVOKE_VIRTUAL_RANGE:
3170        case OP_INVOKE_VIRTUAL_JUMBO: {
3171            MipsLIR *predChainingCell = &labelList[bb->taken->id];
3172            int methodIndex =
3173                cUnit->method->clazz->pDvmDex->pResMethods[dInsn->vB]->
3174                methodIndex;
3175
3176            /*
3177             * If the invoke has non-null misPredBranchOver, we need to generate
3178             * the non-inlined version of the invoke here to handle the
3179             * mispredicted case.
3180             */
3181            if (mir->meta.callsiteInfo->misPredBranchOver) {
3182                genLandingPadForMispredictedCallee(cUnit, mir, bb, labelList);
3183            }
3184
3185            if (mir->dalvikInsn.opcode == OP_INVOKE_VIRTUAL)
3186                genProcessArgsNoRange(cUnit, mir, dInsn, &pcrLabel);
3187            else
3188                genProcessArgsRange(cUnit, mir, dInsn, &pcrLabel);
3189
3190            genInvokeVirtualCommon(cUnit, mir, methodIndex,
3191                                   retChainingCell,
3192                                   predChainingCell,
3193                                   pcrLabel);
3194            break;
3195        }
3196        /*
3197         * calleeMethod = method->clazz->super->vtable[method->clazz->pDvmDex
3198         *                ->pResMethods[BBBB]->methodIndex]
3199         */
3200        case OP_INVOKE_SUPER:
3201        case OP_INVOKE_SUPER_RANGE:
3202        case OP_INVOKE_SUPER_JUMBO: {
3203            /* Grab the method ptr directly from what the interpreter sees */
3204            const Method *calleeMethod = mir->meta.callsiteInfo->method;
3205            assert(calleeMethod == cUnit->method->clazz->super->vtable[
3206                                     cUnit->method->clazz->pDvmDex->
3207                                       pResMethods[dInsn->vB]->methodIndex]);
3208
3209            if (mir->dalvikInsn.opcode == OP_INVOKE_SUPER)
3210                genProcessArgsNoRange(cUnit, mir, dInsn, &pcrLabel);
3211            else
3212                genProcessArgsRange(cUnit, mir, dInsn, &pcrLabel);
3213
3214            if (mir->OptimizationFlags & MIR_INVOKE_METHOD_JIT) {
3215                const Method *calleeMethod = mir->meta.callsiteInfo->method;
3216                void *calleeAddr = dvmJitGetMethodAddr(calleeMethod->insns);
3217                assert(calleeAddr);
3218                genInvokeSingletonWholeMethod(cUnit, mir, calleeAddr,
3219                                              retChainingCell);
3220            } else {
3221                /* r_A0 = calleeMethod */
3222                loadConstant(cUnit, r_A0, (int) calleeMethod);
3223
3224                genInvokeSingletonCommon(cUnit, mir, bb, labelList, pcrLabel,
3225                                         calleeMethod);
3226            }
3227            break;
3228        }
3229        /* calleeMethod = method->clazz->pDvmDex->pResMethods[BBBB] */
3230        case OP_INVOKE_DIRECT:
3231        case OP_INVOKE_DIRECT_RANGE:
3232        case OP_INVOKE_DIRECT_JUMBO: {
3233            /* Grab the method ptr directly from what the interpreter sees */
3234            const Method *calleeMethod = mir->meta.callsiteInfo->method;
3235            assert(calleeMethod ==
3236                   cUnit->method->clazz->pDvmDex->pResMethods[dInsn->vB]);
3237
3238            if (mir->dalvikInsn.opcode == OP_INVOKE_DIRECT)
3239                genProcessArgsNoRange(cUnit, mir, dInsn, &pcrLabel);
3240            else
3241                genProcessArgsRange(cUnit, mir, dInsn, &pcrLabel);
3242
3243            /* r_A0 = calleeMethod */
3244            loadConstant(cUnit, r_A0, (int) calleeMethod);
3245
3246            genInvokeSingletonCommon(cUnit, mir, bb, labelList, pcrLabel,
3247                                     calleeMethod);
3248            break;
3249        }
3250        /* calleeMethod = method->clazz->pDvmDex->pResMethods[BBBB] */
3251        case OP_INVOKE_STATIC:
3252        case OP_INVOKE_STATIC_RANGE:
3253        case OP_INVOKE_STATIC_JUMBO: {
3254            /* Grab the method ptr directly from what the interpreter sees */
3255            const Method *calleeMethod = mir->meta.callsiteInfo->method;
3256            assert(calleeMethod ==
3257                   cUnit->method->clazz->pDvmDex->pResMethods[dInsn->vB]);
3258
3259            if (mir->dalvikInsn.opcode == OP_INVOKE_STATIC)
3260                genProcessArgsNoRange(cUnit, mir, dInsn,
3261                                      NULL /* no null check */);
3262            else
3263                genProcessArgsRange(cUnit, mir, dInsn,
3264                                    NULL /* no null check */);
3265
3266            if (mir->OptimizationFlags & MIR_INVOKE_METHOD_JIT) {
3267                const Method *calleeMethod = mir->meta.callsiteInfo->method;
3268                void *calleeAddr = dvmJitGetMethodAddr(calleeMethod->insns);
3269                assert(calleeAddr);
3270                genInvokeSingletonWholeMethod(cUnit, mir, calleeAddr,
3271                                              retChainingCell);
3272            } else {
3273                /* r_A0 = calleeMethod */
3274                loadConstant(cUnit, r_A0, (int) calleeMethod);
3275
3276                genInvokeSingletonCommon(cUnit, mir, bb, labelList, pcrLabel,
3277                                         calleeMethod);
3278            }
3279            break;
3280        }
3281
3282        /*
3283         * calleeMethod = dvmFindInterfaceMethodInCache(this->clazz,
3284         *                    BBBB, method, method->clazz->pDvmDex)
3285         *
3286         * The following is an example of generated code for
3287         *      "invoke-interface v0"
3288         *
3289         * -------- dalvik offset: 0x000f @ invoke-interface (PI) v2
3290         * 0x2f140c54 : lw       a0,8(s1)                    # genProcessArgsNoRange
3291         * 0x2f140c58 : addiu    s4,s1,0xffffffe8(-24)
3292         * 0x2f140c5c : beqz     a0,0x2f140d5c (L0x11f864)
3293         * 0x2f140c60 : pref     1,0(s4)
3294         * -------- BARRIER
3295         * 0x2f140c64 : sw       a0,0(s4)
3296         * 0x2f140c68 : addiu    s4,s4,0x0004(4)
3297         * -------- BARRIER
3298         * 0x2f140c6c : lui      s0,0x2d23(11555)            # dalvikPC
3299         * 0x2f140c70 : ori      s0,s0,0x2d2365a6(757294502)
3300         * 0x2f140c74 : lahi/lui a1,0x2f14(12052)            # a1 <- &retChainingCell
3301         * 0x2f140c78 : lalo/ori a1,a1,0x2f140d38(789843256)
3302         * 0x2f140c7c : lahi/lui a2,0x2f14(12052)            # a2 <- &predictedChainingCell
3303         * 0x2f140c80 : lalo/ori a2,a2,0x2f140d80(789843328)
3304         * 0x2f140c84 : jal      0x2f1311ec(789778924)       # call TEMPLATE_INVOKE_METHOD_PREDICTED_CHAIN
3305         * 0x2f140c88 : nop
3306         * 0x2f140c8c : b        0x2f140d80 (L0x11efc0)      # off to the predicted chain
3307         * 0x2f140c90 : nop
3308         * 0x2f140c94 : b        0x2f140d60 (L0x12457c)      # punt to the interpreter
3309         * 0x2f140c98 : lui      a0,0x2d23(11555)
3310         * 0x2f140c9c : move     s5,a1                       # prepare for dvmFindInterfaceMethodInCache
3311         * 0x2f140ca0 : move     s6,a2
3312         * 0x2f140ca4 : move     s7,a3
3313         * 0x2f140ca8 : move     a0,a3
3314         * 0x2f140cac : ori      a1,zero,0x2b42(11074)
3315         * 0x2f140cb0 : lui      a2,0x2c92(11410)
3316         * 0x2f140cb4 : ori      a2,a2,0x2c92adf8(747810296)
3317         * 0x2f140cb8 : lui      a3,0x0009(9)
3318         * 0x2f140cbc : ori      a3,a3,0x924b8(599224)
3319         * 0x2f140cc0 : lui      t9,0x2ab2(10930)
3320         * 0x2f140cc4 : ori      t9,t9,0x2ab2a48c(716350604)
3321         * 0x2f140cc8 : jalr     ra,t9                       # call dvmFindInterfaceMethodInCache
3322         * 0x2f140ccc : nop
3323         * 0x2f140cd0 : lw       gp,84(sp)
3324         * 0x2f140cd4 : move     a0,v0
3325         * 0x2f140cd8 : bne      v0,zero,0x2f140cf0 (L0x120064)
3326         * 0x2f140cdc : nop
3327         * 0x2f140ce0 : lui      a0,0x2d23(11555)            # a0 <- dalvikPC
3328         * 0x2f140ce4 : ori      a0,a0,0x2d2365a6(757294502)
3329         * 0x2f140ce8 : jal      0x2f131720(789780256)       # call TEMPLATE_THROW_EXCEPTION_COMMON
3330         * 0x2f140cec : nop
3331         * 0x2f140cf0 : move     a1,s5                       # a1 <- &retChainingCell
3332         * 0x2f140cf4 : bgtz     s5,0x2f140d20 (L0x120324)   # >0? don't rechain
3333         * 0x2f140cf8 : nop
3334         * 0x2f140cfc : lui      t9,0x2aba(10938)            # prepare for dvmJitToPatchPredictedChain
3335         * 0x2f140d00 : ori      t9,t9,0x2abae3c4(716891076)
3336         * 0x2f140d04 : move     a1,s2
3337         * 0x2f140d08 : move     a2,s6
3338         * 0x2f140d0c : move     a3,s7
3339         * 0x2f140d10 : jalr     ra,t9                       # call dvmJitToPatchPredictedChain
3340         * 0x2f140d14 : nop
3341         * 0x2f140d18 : lw       gp,84(sp)
3342         * 0x2f140d1c : move     a0,v0
3343         * 0x2f140d20 : lahi/lui a1,0x2f14(12052)
3344         * 0x2f140d24 : lalo/ori a1,a1,0x2f140d38(789843256) # a1 <- &retChainingCell
3345         * 0x2f140d28 : jal      0x2f1310c4(789778628)       # call TEMPLATE_INVOKE_METHOD_NO_OPT
3346         * 0x2f140d2c : nop
3347         * 0x2f140d30 : b        0x2f140d60 (L0x12457c)
3348         * 0x2f140d34 : lui      a0,0x2d23(11555)
3349         * 0x2f140d38 : .align4
3350         * -------- dalvik offset: 0x0012 @ move-result (PI) v1, (#0), (#0)
3351         * 0x2f140d38 : lw       a2,16(s2)
3352         * 0x2f140d3c : sw       a2,4(s1)
3353         * 0x2f140d40 : b        0x2f140d74 (L0x1246fc)
3354         * 0x2f140d44 : lw       a0,116(s2)
3355         * 0x2f140d48 : undefined
3356         * -------- reconstruct dalvik PC : 0x2d2365a6 @ +0x000f
3357         * 0x2f140d4c : lui      a0,0x2d23(11555)
3358         * 0x2f140d50 : ori      a0,a0,0x2d2365a6(757294502)
3359         * 0x2f140d54 : b        0x2f140d68 (L0x12463c)
3360         * 0x2f140d58 : lw       a1,108(s2)
3361         * -------- reconstruct dalvik PC : 0x2d2365a6 @ +0x000f
3362         * 0x2f140d5c : lui      a0,0x2d23(11555)
3363         * 0x2f140d60 : ori      a0,a0,0x2d2365a6(757294502)
3364         * Exception_Handling:
3365         * 0x2f140d64 : lw       a1,108(s2)
3366         * 0x2f140d68 : jalr     ra,a1
3367         * 0x2f140d6c : nop
3368         * 0x2f140d70 : .align4
3369         * -------- chaining cell (hot): 0x0013
3370         * 0x2f140d70 : lw       a0,116(s2)
3371         * 0x2f140d74 : jalr     ra,a0
3372         * 0x2f140d78 : nop
3373         * 0x2f140d7c : data     0x2d2365ae(757294510)
3374         * 0x2f140d80 : .align4
3375         * -------- chaining cell (predicted): N/A
3376         * 0x2f140d80 : data     0xe7fe(59390)
3377         * 0x2f140d84 : data     0x0000(0)
3378         * 0x2f140d88 : data     0x0000(0)
3379         * 0x2f140d8c : data     0x0000(0)
3380         * 0x2f140d90 : data     0x0000(0)
3381         * -------- end of chaining cells (0x0190)
3382         */
3383        case OP_INVOKE_INTERFACE:
3384        case OP_INVOKE_INTERFACE_RANGE:
3385        case OP_INVOKE_INTERFACE_JUMBO: {
3386            MipsLIR *predChainingCell = &labelList[bb->taken->id];
3387
3388            /*
3389             * If the invoke has non-null misPredBranchOver, we need to generate
3390             * the non-inlined version of the invoke here to handle the
3391             * mispredicted case.
3392             */
3393            if (mir->meta.callsiteInfo->misPredBranchOver) {
3394                genLandingPadForMispredictedCallee(cUnit, mir, bb, labelList);
3395            }
3396
3397            if (mir->dalvikInsn.opcode == OP_INVOKE_INTERFACE)
3398                genProcessArgsNoRange(cUnit, mir, dInsn, &pcrLabel);
3399            else
3400                genProcessArgsRange(cUnit, mir, dInsn, &pcrLabel);
3401
3402            /* "this" is already left in r_A0 by genProcessArgs* */
3403
3404            /* r4PC = dalvikCallsite */
3405            loadConstant(cUnit, r4PC,
3406                         (int) (cUnit->method->insns + mir->offset));
3407
3408            /* r_A1 = &retChainingCell */
3409            MipsLIR *addrRetChain = newLIR2(cUnit, kMipsLahi, r_A1, 0);
3410            addrRetChain->generic.target = (LIR *) retChainingCell;
3411            addrRetChain = newLIR3(cUnit, kMipsLalo, r_A1, r_A1, 0);
3412            addrRetChain->generic.target = (LIR *) retChainingCell;
3413
3414
3415            /* r_A2 = &predictedChainingCell */
3416            MipsLIR *predictedChainingCell = newLIR2(cUnit, kMipsLahi, r_A2, 0);
3417            predictedChainingCell->generic.target = (LIR *) predChainingCell;
3418            predictedChainingCell = newLIR3(cUnit, kMipsLalo, r_A2, r_A2, 0);
3419            predictedChainingCell->generic.target = (LIR *) predChainingCell;
3420
3421            genDispatchToHandler(cUnit, gDvmJit.methodTraceSupport ?
3422                TEMPLATE_INVOKE_METHOD_PREDICTED_CHAIN_PROF :
3423                TEMPLATE_INVOKE_METHOD_PREDICTED_CHAIN);
3424
3425            /* return through ra - jump to the chaining cell */
3426            genUnconditionalBranch(cUnit, predChainingCell);
3427
3428            /*
3429             * null-check on "this" may have been eliminated, but we still need
3430             * a PC-reconstruction label for stack overflow bailout.
3431             */
3432            if (pcrLabel == NULL) {
3433                int dPC = (int) (cUnit->method->insns + mir->offset);
3434                pcrLabel = (MipsLIR *) dvmCompilerNew(sizeof(MipsLIR), true);
3435                pcrLabel->opcode = kMipsPseudoPCReconstructionCell;
3436                pcrLabel->operands[0] = dPC;
3437                pcrLabel->operands[1] = mir->offset;
3438                /* Insert the place holder to the growable list */
3439                dvmInsertGrowableList(&cUnit->pcReconstructionList,
3440                                      (intptr_t) pcrLabel);
3441            }
3442
3443            /* return through ra+8 - punt to the interpreter */
3444            genUnconditionalBranch(cUnit, pcrLabel);
3445
3446            /*
3447             * return through ra+16 - fully resolve the callee method.
3448             * r_A1 <- count
3449             * r_A2 <- &predictedChainCell
3450             * r_A3 <- this->class
3451             * r4 <- dPC
3452             * r_S4 <- this->class->vtable
3453             */
3454
3455            /* Save count, &predictedChainCell, and class to high regs first */
3456            genRegCopy(cUnit, r_S5, r_A1);
3457            genRegCopy(cUnit, r_S6, r_A2);
3458            genRegCopy(cUnit, r_S7, r_A3);
3459
3460            /* r_A0 now contains this->clazz */
3461            genRegCopy(cUnit, r_A0, r_A3);
3462
3463            /* r_A1 = BBBB */
3464            loadConstant(cUnit, r_A1, dInsn->vB);
3465
3466            /* r_A2 = method (caller) */
3467            loadConstant(cUnit, r_A2, (int) cUnit->method);
3468
3469            /* r_A3 = pDvmDex */
3470            loadConstant(cUnit, r_A3, (int) cUnit->method->clazz->pDvmDex);
3471
3472            LOAD_FUNC_ADDR(cUnit, r_T9,
3473                           (intptr_t) dvmFindInterfaceMethodInCache);
3474            opReg(cUnit, kOpBlx, r_T9);
3475            newLIR3(cUnit, kMipsLw, r_GP, STACK_OFFSET_GP, r_SP);
3476            /* r_V0 = calleeMethod (returned from dvmFindInterfaceMethodInCache */
3477            genRegCopy(cUnit, r_A0, r_V0);
3478
3479            dvmCompilerClobberCallRegs(cUnit);
3480            /* generate a branch over if the interface method is resolved */
3481            MipsLIR *branchOver = opCompareBranch(cUnit, kMipsBne, r_V0, r_ZERO);
3482            /*
3483             * calleeMethod == NULL -> throw
3484             */
3485            loadConstant(cUnit, r_A0,
3486                         (int) (cUnit->method->insns + mir->offset));
3487            genDispatchToHandler(cUnit, TEMPLATE_THROW_EXCEPTION_COMMON);
3488            /* noreturn */
3489
3490            MipsLIR *target = newLIR0(cUnit, kMipsPseudoTargetLabel);
3491            target->defMask = ENCODE_ALL;
3492            branchOver->generic.target = (LIR *) target;
3493
3494            genRegCopy(cUnit, r_A1, r_S5);
3495
3496            /* Check if rechain limit is reached */
3497            MipsLIR *bypassRechaining = opCompareBranch(cUnit, kMipsBgtz, r_S5, -1);
3498
3499            LOAD_FUNC_ADDR(cUnit, r_T9, (int) dvmJitToPatchPredictedChain);
3500
3501            genRegCopy(cUnit, r_A1, rSELF);
3502            genRegCopy(cUnit, r_A2, r_S6);
3503            genRegCopy(cUnit, r_A3, r_S7);
3504
3505            /*
3506             * r_A0 = calleeMethod
3507             * r_A2 = &predictedChainingCell
3508             * r_A3 = class
3509             *
3510             * &returnChainingCell has been loaded into r_A1 but is not needed
3511             * when patching the chaining cell and will be clobbered upon
3512             * returning so it will be reconstructed again.
3513             */
3514            opReg(cUnit, kOpBlx, r_T9);
3515            newLIR3(cUnit, kMipsLw, r_GP, STACK_OFFSET_GP, r_SP);
3516            genRegCopy(cUnit, r_A0, r_V0);
3517
3518            /* r_A1 = &retChainingCell */
3519            addrRetChain = newLIR2(cUnit, kMipsLahi, r_A1, 0);
3520            addrRetChain->generic.target = (LIR *) retChainingCell;
3521            bypassRechaining->generic.target = (LIR *) addrRetChain;
3522            addrRetChain = newLIR3(cUnit, kMipsLalo, r_A1, r_A1, 0);
3523            addrRetChain->generic.target = (LIR *) retChainingCell;
3524
3525
3526            /*
3527             * r_A0 = this, r_A1 = calleeMethod,
3528             * r_A1 = &ChainingCell,
3529             * r4PC = callsiteDPC,
3530             */
3531            genDispatchToHandler(cUnit, gDvmJit.methodTraceSupport ?
3532                TEMPLATE_INVOKE_METHOD_NO_OPT_PROF :
3533                TEMPLATE_INVOKE_METHOD_NO_OPT);
3534
3535#if defined(WITH_JIT_TUNING)
3536            gDvmJit.invokePolymorphic++;
3537#endif
3538            /* Handle exceptions using the interpreter */
3539            genTrap(cUnit, mir->offset, pcrLabel);
3540            break;
3541        }
3542        case OP_INVOKE_OBJECT_INIT_JUMBO:
3543        case OP_INVOKE_OBJECT_INIT_RANGE:
3544        case OP_FILLED_NEW_ARRAY:
3545        case OP_FILLED_NEW_ARRAY_RANGE:
3546        case OP_FILLED_NEW_ARRAY_JUMBO: {
3547            /* Just let the interpreter deal with these */
3548            genInterpSingleStep(cUnit, mir);
3549            break;
3550        }
3551        default:
3552            return true;
3553    }
3554    return false;
3555}
3556
3557static bool handleFmt35ms_3rms(CompilationUnit *cUnit, MIR *mir,
3558                               BasicBlock *bb, MipsLIR *labelList)
3559{
3560    MipsLIR *pcrLabel = NULL;
3561
3562    /* An invoke with the MIR_INLINED is effectively a no-op */
3563    if (mir->OptimizationFlags & MIR_INLINED)
3564        return false;
3565
3566    DecodedInstruction *dInsn = &mir->dalvikInsn;
3567    switch (mir->dalvikInsn.opcode) {
3568        /* calleeMethod = this->clazz->vtable[BBBB] */
3569        case OP_INVOKE_VIRTUAL_QUICK_RANGE:
3570        case OP_INVOKE_VIRTUAL_QUICK: {
3571            int methodIndex = dInsn->vB;
3572            MipsLIR *retChainingCell = &labelList[bb->fallThrough->id];
3573            MipsLIR *predChainingCell = &labelList[bb->taken->id];
3574
3575            /*
3576             * If the invoke has non-null misPredBranchOver, we need to generate
3577             * the non-inlined version of the invoke here to handle the
3578             * mispredicted case.
3579             */
3580            if (mir->meta.callsiteInfo->misPredBranchOver) {
3581                genLandingPadForMispredictedCallee(cUnit, mir, bb, labelList);
3582            }
3583
3584            if (mir->dalvikInsn.opcode == OP_INVOKE_VIRTUAL_QUICK)
3585                genProcessArgsNoRange(cUnit, mir, dInsn, &pcrLabel);
3586            else
3587                genProcessArgsRange(cUnit, mir, dInsn, &pcrLabel);
3588
3589            if (mir->OptimizationFlags & MIR_INVOKE_METHOD_JIT) {
3590                const Method *calleeMethod = mir->meta.callsiteInfo->method;
3591                void *calleeAddr = dvmJitGetMethodAddr(calleeMethod->insns);
3592                assert(calleeAddr);
3593                genInvokeVirtualWholeMethod(cUnit, mir, calleeAddr,
3594                                            retChainingCell);
3595            }
3596
3597            genInvokeVirtualCommon(cUnit, mir, methodIndex,
3598                                   retChainingCell,
3599                                   predChainingCell,
3600                                   pcrLabel);
3601            break;
3602        }
3603        /* calleeMethod = method->clazz->super->vtable[BBBB] */
3604        case OP_INVOKE_SUPER_QUICK:
3605        case OP_INVOKE_SUPER_QUICK_RANGE: {
3606            /* Grab the method ptr directly from what the interpreter sees */
3607            const Method *calleeMethod = mir->meta.callsiteInfo->method;
3608            assert(calleeMethod ==
3609                   cUnit->method->clazz->super->vtable[dInsn->vB]);
3610
3611            if (mir->dalvikInsn.opcode == OP_INVOKE_SUPER_QUICK)
3612                genProcessArgsNoRange(cUnit, mir, dInsn, &pcrLabel);
3613            else
3614                genProcessArgsRange(cUnit, mir, dInsn, &pcrLabel);
3615
3616            /* r_A0 = calleeMethod */
3617            loadConstant(cUnit, r_A0, (int) calleeMethod);
3618
3619            genInvokeSingletonCommon(cUnit, mir, bb, labelList, pcrLabel,
3620                                     calleeMethod);
3621            break;
3622        }
3623        default:
3624            return true;
3625    }
3626    return false;
3627}
3628
3629/*
3630 * This operation is complex enough that we'll do it partly inline
3631 * and partly with a handler.  NOTE: the handler uses hardcoded
3632 * values for string object offsets and must be revisitied if the
3633 * layout changes.
3634 */
3635static bool genInlinedCompareTo(CompilationUnit *cUnit, MIR *mir)
3636{
3637#if defined(USE_GLOBAL_STRING_DEFS)
3638    return handleExecuteInlineC(cUnit, mir);
3639#else
3640    MipsLIR *rollback;
3641    RegLocation rlThis = dvmCompilerGetSrc(cUnit, mir, 0);
3642    RegLocation rlComp = dvmCompilerGetSrc(cUnit, mir, 1);
3643
3644    loadValueDirectFixed(cUnit, rlThis, r_A0);
3645    loadValueDirectFixed(cUnit, rlComp, r_A1);
3646    /* Test objects for NULL */
3647    rollback = genNullCheck(cUnit, rlThis.sRegLow, r_A0, mir->offset, NULL);
3648    genNullCheck(cUnit, rlComp.sRegLow, r_A1, mir->offset, rollback);
3649    /*
3650     * TUNING: we could check for object pointer equality before invoking
3651     * handler. Unclear whether the gain would be worth the added code size
3652     * expansion.
3653     */
3654    genDispatchToHandler(cUnit, TEMPLATE_STRING_COMPARETO);
3655    storeValue(cUnit, inlinedTarget(cUnit, mir, false),
3656               dvmCompilerGetReturn(cUnit));
3657    return false;
3658#endif
3659}
3660
3661static bool genInlinedFastIndexOf(CompilationUnit *cUnit, MIR *mir)
3662{
3663#if defined(USE_GLOBAL_STRING_DEFS)
3664    return handleExecuteInlineC(cUnit, mir);
3665#else
3666    RegLocation rlThis = dvmCompilerGetSrc(cUnit, mir, 0);
3667    RegLocation rlChar = dvmCompilerGetSrc(cUnit, mir, 1);
3668
3669    loadValueDirectFixed(cUnit, rlThis, r_A0);
3670    loadValueDirectFixed(cUnit, rlChar, r_A1);
3671
3672    RegLocation rlStart = dvmCompilerGetSrc(cUnit, mir, 2);
3673    loadValueDirectFixed(cUnit, rlStart, r_A2);
3674
3675    /* Test objects for NULL */
3676    genNullCheck(cUnit, rlThis.sRegLow, r_A0, mir->offset, NULL);
3677    genDispatchToHandler(cUnit, TEMPLATE_STRING_INDEXOF);
3678    storeValue(cUnit, inlinedTarget(cUnit, mir, false),
3679               dvmCompilerGetReturn(cUnit));
3680    return false;
3681#endif
3682}
3683
3684// Generates an inlined String.isEmpty or String.length.
3685static bool genInlinedStringIsEmptyOrLength(CompilationUnit *cUnit, MIR *mir,
3686                                            bool isEmpty)
3687{
3688    // dst = src.length();
3689    RegLocation rlObj = dvmCompilerGetSrc(cUnit, mir, 0);
3690    RegLocation rlDest = inlinedTarget(cUnit, mir, false);
3691    rlObj = loadValue(cUnit, rlObj, kCoreReg);
3692    RegLocation rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
3693    genNullCheck(cUnit, rlObj.sRegLow, rlObj.lowReg, mir->offset, NULL);
3694    loadWordDisp(cUnit, rlObj.lowReg, gDvm.offJavaLangString_count,
3695                 rlResult.lowReg);
3696    if (isEmpty) {
3697        // dst = (dst == 0);
3698        int tReg = dvmCompilerAllocTemp(cUnit);
3699        newLIR3(cUnit, kMipsSltu, tReg, r_ZERO, rlResult.lowReg);
3700        opRegRegImm(cUnit, kOpXor, rlResult.lowReg, tReg, 1);
3701    }
3702    storeValue(cUnit, rlDest, rlResult);
3703    return false;
3704}
3705
3706static bool genInlinedStringLength(CompilationUnit *cUnit, MIR *mir)
3707{
3708    return genInlinedStringIsEmptyOrLength(cUnit, mir, false);
3709}
3710
3711static bool genInlinedStringIsEmpty(CompilationUnit *cUnit, MIR *mir)
3712{
3713    return genInlinedStringIsEmptyOrLength(cUnit, mir, true);
3714}
3715
3716static bool genInlinedStringCharAt(CompilationUnit *cUnit, MIR *mir)
3717{
3718    int contents = OFFSETOF_MEMBER(ArrayObject, contents);
3719    RegLocation rlObj = dvmCompilerGetSrc(cUnit, mir, 0);
3720    RegLocation rlIdx = dvmCompilerGetSrc(cUnit, mir, 1);
3721    RegLocation rlDest = inlinedTarget(cUnit, mir, false);
3722    RegLocation rlResult;
3723    rlObj = loadValue(cUnit, rlObj, kCoreReg);
3724    rlIdx = loadValue(cUnit, rlIdx, kCoreReg);
3725    int regMax = dvmCompilerAllocTemp(cUnit);
3726    int regOff = dvmCompilerAllocTemp(cUnit);
3727    int regPtr = dvmCompilerAllocTemp(cUnit);
3728    MipsLIR *pcrLabel = genNullCheck(cUnit, rlObj.sRegLow, rlObj.lowReg,
3729                                    mir->offset, NULL);
3730    loadWordDisp(cUnit, rlObj.lowReg, gDvm.offJavaLangString_count, regMax);
3731    loadWordDisp(cUnit, rlObj.lowReg, gDvm.offJavaLangString_offset, regOff);
3732    loadWordDisp(cUnit, rlObj.lowReg, gDvm.offJavaLangString_value, regPtr);
3733    genBoundsCheck(cUnit, rlIdx.lowReg, regMax, mir->offset, pcrLabel);
3734    dvmCompilerFreeTemp(cUnit, regMax);
3735    opRegImm(cUnit, kOpAdd, regPtr, contents);
3736    opRegReg(cUnit, kOpAdd, regOff, rlIdx.lowReg);
3737    rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
3738    loadBaseIndexed(cUnit, regPtr, regOff, rlResult.lowReg, 1, kUnsignedHalf);
3739    storeValue(cUnit, rlDest, rlResult);
3740    return false;
3741}
3742
3743static bool genInlinedAbsInt(CompilationUnit *cUnit, MIR *mir)
3744{
3745    RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
3746    rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
3747    RegLocation rlDest = inlinedTarget(cUnit, mir, false);
3748    RegLocation rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
3749    int signReg = dvmCompilerAllocTemp(cUnit);
3750    /*
3751     * abs(x) = y<=x>>31, (x+y)^y.
3752     * Thumb2's IT block also yields 3 instructions, but imposes
3753     * scheduling constraints.
3754     */
3755    opRegRegImm(cUnit, kOpAsr, signReg, rlSrc.lowReg, 31);
3756    opRegRegReg(cUnit, kOpAdd, rlResult.lowReg, rlSrc.lowReg, signReg);
3757    opRegReg(cUnit, kOpXor, rlResult.lowReg, signReg);
3758    storeValue(cUnit, rlDest, rlResult);
3759    return false;
3760}
3761
3762static bool genInlinedAbsLong(CompilationUnit *cUnit, MIR *mir)
3763{
3764    RegLocation rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
3765    RegLocation rlDest = inlinedTargetWide(cUnit, mir, false);
3766    rlSrc = loadValueWide(cUnit, rlSrc, kCoreReg);
3767    RegLocation rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
3768    int signReg = dvmCompilerAllocTemp(cUnit);
3769    int tReg = dvmCompilerAllocTemp(cUnit);
3770    /*
3771     * abs(x) = y<=x>>31, (x+y)^y.
3772     * Thumb2 IT block allows slightly shorter sequence,
3773     * but introduces a scheduling barrier.  Stick with this
3774     * mechanism for now.
3775     */
3776    opRegRegImm(cUnit, kOpAsr, signReg, rlSrc.highReg, 31);
3777    opRegRegReg(cUnit, kOpAdd, rlResult.lowReg, rlSrc.lowReg, signReg);
3778    newLIR3(cUnit, kMipsSltu, tReg, rlResult.lowReg, signReg);
3779    opRegRegReg(cUnit, kOpAdd, rlResult.highReg, rlSrc.highReg, signReg);
3780    opRegRegReg(cUnit, kOpAdd, rlResult.highReg, rlResult.highReg, tReg);
3781    opRegReg(cUnit, kOpXor, rlResult.lowReg, signReg);
3782    opRegReg(cUnit, kOpXor, rlResult.highReg, signReg);
3783    dvmCompilerFreeTemp(cUnit, signReg);
3784    dvmCompilerFreeTemp(cUnit, tReg);
3785    storeValueWide(cUnit, rlDest, rlResult);
3786    return false;
3787}
3788
3789static bool genInlinedIntFloatConversion(CompilationUnit *cUnit, MIR *mir)
3790{
3791    // Just move from source to destination...
3792    RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
3793    RegLocation rlDest = inlinedTarget(cUnit, mir, false);
3794    storeValue(cUnit, rlDest, rlSrc);
3795    return false;
3796}
3797
3798static bool genInlinedLongDoubleConversion(CompilationUnit *cUnit, MIR *mir)
3799{
3800    // Just move from source to destination...
3801    RegLocation rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
3802    RegLocation rlDest = inlinedTargetWide(cUnit, mir, false);
3803    storeValueWide(cUnit, rlDest, rlSrc);
3804    return false;
3805}
3806/*
3807 * JITs a call to a C function.
3808 * TODO: use this for faster native method invocation for simple native
3809 * methods (http://b/3069458).
3810 */
3811static bool handleExecuteInlineC(CompilationUnit *cUnit, MIR *mir)
3812{
3813    DecodedInstruction *dInsn = &mir->dalvikInsn;
3814    int operation = dInsn->vB;
3815    unsigned int i;
3816    const InlineOperation* inLineTable = dvmGetInlineOpsTable();
3817    uintptr_t fn = (int) inLineTable[operation].func;
3818    if (fn == 0) {
3819        dvmCompilerAbort(cUnit);
3820    }
3821    dvmCompilerFlushAllRegs(cUnit);   /* Everything to home location */
3822    dvmCompilerClobberCallRegs(cUnit);
3823    dvmCompilerClobber(cUnit, r4PC);
3824    dvmCompilerClobber(cUnit, rINST);
3825    int offset = offsetof(Thread, interpSave.retval);
3826    opRegRegImm(cUnit, kOpAdd, r4PC, rSELF, offset);
3827    newLIR3(cUnit, kMipsSw, r4PC, 16, r_SP); /* sp has plenty of space */
3828    genExportPC(cUnit, mir);
3829    assert(dInsn->vA <= 4);
3830    for (i=0; i < dInsn->vA; i++) {
3831        loadValueDirect(cUnit, dvmCompilerGetSrc(cUnit, mir, i), i+r_A0);
3832    }
3833    LOAD_FUNC_ADDR(cUnit, r_T9, fn);
3834    opReg(cUnit, kOpBlx, r_T9);
3835    newLIR3(cUnit, kMipsLw, r_GP, STACK_OFFSET_GP, r_SP);
3836    /* NULL? */
3837    MipsLIR *branchOver = opCompareBranch(cUnit, kMipsBne, r_V0, r_ZERO);
3838    loadConstant(cUnit, r_A0, (int) (cUnit->method->insns + mir->offset));
3839    genDispatchToHandler(cUnit, TEMPLATE_THROW_EXCEPTION_COMMON);
3840    MipsLIR *target = newLIR0(cUnit, kMipsPseudoTargetLabel);
3841    target->defMask = ENCODE_ALL;
3842    branchOver->generic.target = (LIR *) target;
3843    return false;
3844}
3845
3846/*
3847 * NOTE: Handles both range and non-range versions (arguments
3848 * have already been normalized by this point).
3849 */
3850static bool handleExecuteInline(CompilationUnit *cUnit, MIR *mir)
3851{
3852    DecodedInstruction *dInsn = &mir->dalvikInsn;
3853    assert(dInsn->opcode == OP_EXECUTE_INLINE_RANGE ||
3854           dInsn->opcode == OP_EXECUTE_INLINE);
3855    switch (dInsn->vB) {
3856        case INLINE_EMPTYINLINEMETHOD:
3857            return false;  /* Nop */
3858
3859        /* These ones we potentially JIT inline. */
3860        case INLINE_STRING_LENGTH:
3861            return genInlinedStringLength(cUnit, mir);
3862        case INLINE_STRING_IS_EMPTY:
3863            return genInlinedStringIsEmpty(cUnit, mir);
3864        case INLINE_MATH_ABS_INT:
3865            return genInlinedAbsInt(cUnit, mir);
3866        case INLINE_MATH_ABS_LONG:
3867            return genInlinedAbsLong(cUnit, mir);
3868        case INLINE_MATH_MIN_INT:
3869            return genInlinedMinMaxInt(cUnit, mir, true);
3870        case INLINE_MATH_MAX_INT:
3871            return genInlinedMinMaxInt(cUnit, mir, false);
3872        case INLINE_STRING_CHARAT:
3873            return genInlinedStringCharAt(cUnit, mir);
3874        case INLINE_MATH_SQRT:
3875            return genInlineSqrt(cUnit, mir);
3876        case INLINE_MATH_ABS_FLOAT:
3877            return genInlinedAbsFloat(cUnit, mir);
3878        case INLINE_MATH_ABS_DOUBLE:
3879            return genInlinedAbsDouble(cUnit, mir);
3880        case INLINE_STRING_COMPARETO:
3881            return genInlinedCompareTo(cUnit, mir);
3882        case INLINE_STRING_FASTINDEXOF_II:
3883            return genInlinedFastIndexOf(cUnit, mir);
3884        case INLINE_FLOAT_TO_RAW_INT_BITS:
3885        case INLINE_INT_BITS_TO_FLOAT:
3886            return genInlinedIntFloatConversion(cUnit, mir);
3887        case INLINE_DOUBLE_TO_RAW_LONG_BITS:
3888        case INLINE_LONG_BITS_TO_DOUBLE:
3889            return genInlinedLongDoubleConversion(cUnit, mir);
3890
3891        /*
3892         * These ones we just JIT a call to a C function for.
3893         * TODO: special-case these in the other "invoke" call paths.
3894         */
3895        case INLINE_STRING_EQUALS:
3896        case INLINE_MATH_COS:
3897        case INLINE_MATH_SIN:
3898        case INLINE_FLOAT_TO_INT_BITS:
3899        case INLINE_DOUBLE_TO_LONG_BITS:
3900            return handleExecuteInlineC(cUnit, mir);
3901    }
3902    dvmCompilerAbort(cUnit);
3903    return false; // Not reachable; keeps compiler happy.
3904}
3905
3906static bool handleFmt51l(CompilationUnit *cUnit, MIR *mir)
3907{
3908    //TUNING: We're using core regs here - not optimal when target is a double
3909    RegLocation rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
3910    RegLocation rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
3911    loadConstantNoClobber(cUnit, rlResult.lowReg,
3912                          mir->dalvikInsn.vB_wide & 0xFFFFFFFFUL);
3913    loadConstantNoClobber(cUnit, rlResult.highReg,
3914                          (mir->dalvikInsn.vB_wide>>32) & 0xFFFFFFFFUL);
3915    storeValueWide(cUnit, rlDest, rlResult);
3916    return false;
3917}
3918
3919/*
3920 * The following are special processing routines that handle transfer of
3921 * controls between compiled code and the interpreter. Certain VM states like
3922 * Dalvik PC and special-purpose registers are reconstructed here.
3923 */
3924
3925/* Chaining cell for code that may need warmup. */
3926static void handleNormalChainingCell(CompilationUnit *cUnit,
3927                                     unsigned int offset)
3928{
3929    newLIR3(cUnit, kMipsLw, r_A0,
3930        offsetof(Thread, jitToInterpEntries.dvmJitToInterpNormal),
3931        rSELF);
3932    newLIR2(cUnit, kMipsJalr, r_RA, r_A0);
3933    addWordData(cUnit, NULL, (int) (cUnit->method->insns + offset));
3934}
3935
3936/*
3937 * Chaining cell for instructions that immediately following already translated
3938 * code.
3939 */
3940static void handleHotChainingCell(CompilationUnit *cUnit,
3941                                  unsigned int offset)
3942{
3943    newLIR3(cUnit, kMipsLw, r_A0,
3944        offsetof(Thread, jitToInterpEntries.dvmJitToInterpTraceSelect),
3945        rSELF);
3946    newLIR2(cUnit, kMipsJalr, r_RA, r_A0);
3947    addWordData(cUnit, NULL, (int) (cUnit->method->insns + offset));
3948}
3949
3950/* Chaining cell for branches that branch back into the same basic block */
3951static void handleBackwardBranchChainingCell(CompilationUnit *cUnit,
3952                                             unsigned int offset)
3953{
3954    /*
3955     * Use raw instruction constructors to guarantee that the generated
3956     * instructions fit the predefined cell size.
3957     */
3958#if defined(WITH_SELF_VERIFICATION)
3959    newLIR3(cUnit, kMipsLw, r_A0,
3960        offsetof(Thread, jitToInterpEntries.dvmJitToInterpBackwardBranch),
3961        rSELF);
3962#else
3963    newLIR3(cUnit, kMipsLw, r_A0,
3964        offsetof(Thread, jitToInterpEntries.dvmJitToInterpNormal),
3965        rSELF);
3966#endif
3967    newLIR2(cUnit, kMipsJalr, r_RA, r_A0);
3968    addWordData(cUnit, NULL, (int) (cUnit->method->insns + offset));
3969}
3970
3971/* Chaining cell for monomorphic method invocations. */
3972static void handleInvokeSingletonChainingCell(CompilationUnit *cUnit,
3973                                              const Method *callee)
3974{
3975    newLIR3(cUnit, kMipsLw, r_A0,
3976        offsetof(Thread, jitToInterpEntries.dvmJitToInterpTraceSelect),
3977        rSELF);
3978    newLIR2(cUnit, kMipsJalr, r_RA, r_A0);
3979    addWordData(cUnit, NULL, (int) (callee->insns));
3980}
3981
3982/* Chaining cell for monomorphic method invocations. */
3983static void handleInvokePredictedChainingCell(CompilationUnit *cUnit)
3984{
3985    /* Should not be executed in the initial state */
3986    addWordData(cUnit, NULL, PREDICTED_CHAIN_BX_PAIR_INIT);
3987    /* branch delay slot nop */
3988    addWordData(cUnit, NULL, PREDICTED_CHAIN_DELAY_SLOT_INIT);
3989    /* To be filled: class */
3990    addWordData(cUnit, NULL, PREDICTED_CHAIN_CLAZZ_INIT);
3991    /* To be filled: method */
3992    addWordData(cUnit, NULL, PREDICTED_CHAIN_METHOD_INIT);
3993    /*
3994     * Rechain count. The initial value of 0 here will trigger chaining upon
3995     * the first invocation of this callsite.
3996     */
3997    addWordData(cUnit, NULL, PREDICTED_CHAIN_COUNTER_INIT);
3998}
3999
4000/* Load the Dalvik PC into a0 and jump to the specified target */
4001static void handlePCReconstruction(CompilationUnit *cUnit,
4002                                   MipsLIR *targetLabel)
4003{
4004    MipsLIR **pcrLabel =
4005        (MipsLIR **) cUnit->pcReconstructionList.elemList;
4006    int numElems = cUnit->pcReconstructionList.numUsed;
4007    int i;
4008
4009    /*
4010     * We should never reach here through fall-through code, so insert
4011     * a bomb to signal troubles immediately.
4012     */
4013    if (numElems) {
4014        newLIR0(cUnit, kMipsUndefined);
4015    }
4016
4017    for (i = 0; i < numElems; i++) {
4018        dvmCompilerAppendLIR(cUnit, (LIR *) pcrLabel[i]);
4019        /* a0 = dalvik PC */
4020        loadConstant(cUnit, r_A0, pcrLabel[i]->operands[0]);
4021        genUnconditionalBranch(cUnit, targetLabel);
4022    }
4023}
4024
4025static const char *extendedMIROpNames[kMirOpLast - kMirOpFirst] = {
4026    "kMirOpPhi",
4027    "kMirOpNullNRangeUpCheck",
4028    "kMirOpNullNRangeDownCheck",
4029    "kMirOpLowerBound",
4030    "kMirOpPunt",
4031    "kMirOpCheckInlinePrediction",
4032};
4033
4034/*
4035 * vA = arrayReg;
4036 * vB = idxReg;
4037 * vC = endConditionReg;
4038 * arg[0] = maxC
4039 * arg[1] = minC
4040 * arg[2] = loopBranchConditionCode
4041 */
4042static void genHoistedChecksForCountUpLoop(CompilationUnit *cUnit, MIR *mir)
4043{
4044    /*
4045     * NOTE: these synthesized blocks don't have ssa names assigned
4046     * for Dalvik registers.  However, because they dominate the following
4047     * blocks we can simply use the Dalvik name w/ subscript 0 as the
4048     * ssa name.
4049     */
4050    DecodedInstruction *dInsn = &mir->dalvikInsn;
4051    const int lenOffset = OFFSETOF_MEMBER(ArrayObject, length);
4052    const int maxC = dInsn->arg[0];
4053    int regLength;
4054    RegLocation rlArray = cUnit->regLocation[mir->dalvikInsn.vA];
4055    RegLocation rlIdxEnd = cUnit->regLocation[mir->dalvikInsn.vC];
4056
4057    /* regArray <- arrayRef */
4058    rlArray = loadValue(cUnit, rlArray, kCoreReg);
4059    rlIdxEnd = loadValue(cUnit, rlIdxEnd, kCoreReg);
4060    genRegImmCheck(cUnit, kMipsCondEq, rlArray.lowReg, 0, 0,
4061                   (MipsLIR *) cUnit->loopAnalysis->branchToPCR);
4062
4063    /* regLength <- len(arrayRef) */
4064    regLength = dvmCompilerAllocTemp(cUnit);
4065    loadWordDisp(cUnit, rlArray.lowReg, lenOffset, regLength);
4066
4067    int delta = maxC;
4068    /*
4069     * If the loop end condition is ">=" instead of ">", then the largest value
4070     * of the index is "endCondition - 1".
4071     */
4072    if (dInsn->arg[2] == OP_IF_GE) {
4073        delta--;
4074    }
4075
4076    if (delta) {
4077        int tReg = dvmCompilerAllocTemp(cUnit);
4078        opRegRegImm(cUnit, kOpAdd, tReg, rlIdxEnd.lowReg, delta);
4079        rlIdxEnd.lowReg = tReg;
4080        dvmCompilerFreeTemp(cUnit, tReg);
4081    }
4082    /* Punt if "regIdxEnd < len(Array)" is false */
4083    genRegRegCheck(cUnit, kMipsCondGe, rlIdxEnd.lowReg, regLength, 0,
4084                   (MipsLIR *) cUnit->loopAnalysis->branchToPCR);
4085}
4086
4087/*
4088 * vA = arrayReg;
4089 * vB = idxReg;
4090 * vC = endConditionReg;
4091 * arg[0] = maxC
4092 * arg[1] = minC
4093 * arg[2] = loopBranchConditionCode
4094 */
4095static void genHoistedChecksForCountDownLoop(CompilationUnit *cUnit, MIR *mir)
4096{
4097    DecodedInstruction *dInsn = &mir->dalvikInsn;
4098    const int lenOffset = OFFSETOF_MEMBER(ArrayObject, length);
4099    const int regLength = dvmCompilerAllocTemp(cUnit);
4100    const int maxC = dInsn->arg[0];
4101    RegLocation rlArray = cUnit->regLocation[mir->dalvikInsn.vA];
4102    RegLocation rlIdxInit = cUnit->regLocation[mir->dalvikInsn.vB];
4103
4104    /* regArray <- arrayRef */
4105    rlArray = loadValue(cUnit, rlArray, kCoreReg);
4106    rlIdxInit = loadValue(cUnit, rlIdxInit, kCoreReg);
4107    genRegImmCheck(cUnit, kMipsCondEq, rlArray.lowReg, 0, 0,
4108                   (MipsLIR *) cUnit->loopAnalysis->branchToPCR);
4109
4110    /* regLength <- len(arrayRef) */
4111    loadWordDisp(cUnit, rlArray.lowReg, lenOffset, regLength);
4112
4113    if (maxC) {
4114        int tReg = dvmCompilerAllocTemp(cUnit);
4115        opRegRegImm(cUnit, kOpAdd, tReg, rlIdxInit.lowReg, maxC);
4116        rlIdxInit.lowReg = tReg;
4117        dvmCompilerFreeTemp(cUnit, tReg);
4118    }
4119
4120    /* Punt if "regIdxInit < len(Array)" is false */
4121    genRegRegCheck(cUnit, kMipsCondGe, rlIdxInit.lowReg, regLength, 0,
4122                   (MipsLIR *) cUnit->loopAnalysis->branchToPCR);
4123}
4124
4125/*
4126 * vA = idxReg;
4127 * vB = minC;
4128 */
4129static void genHoistedLowerBoundCheck(CompilationUnit *cUnit, MIR *mir)
4130{
4131    DecodedInstruction *dInsn = &mir->dalvikInsn;
4132    const int minC = dInsn->vB;
4133    RegLocation rlIdx = cUnit->regLocation[mir->dalvikInsn.vA];
4134
4135    /* regIdx <- initial index value */
4136    rlIdx = loadValue(cUnit, rlIdx, kCoreReg);
4137
4138    /* Punt if "regIdxInit + minC >= 0" is false */
4139    genRegImmCheck(cUnit, kMipsCondLt, rlIdx.lowReg, -minC, 0,
4140                   (MipsLIR *) cUnit->loopAnalysis->branchToPCR);
4141}
4142
4143/*
4144 * vC = this
4145 *
4146 * A predicted inlining target looks like the following, where instructions
4147 * between 0x2f130d24 and 0x2f130d40 are checking if the predicted class
4148 * matches "this", and the verificaion code is generated by this routine.
4149 *
4150 * (C) means the instruction is inlined from the callee, and (PI) means the
4151 * instruction is the predicted inlined invoke, whose corresponding
4152 * instructions are still generated to handle the mispredicted case.
4153 *
4154 * D/dalvikvm( 2377): -------- kMirOpCheckInlinePrediction
4155 * D/dalvikvm( 2377): 0x2f130d24 (0020):  lw       v0,16(s1)
4156 * D/dalvikvm( 2377): 0x2f130d28 (0024):  lui      v1,0x0011(17)
4157 * D/dalvikvm( 2377): 0x2f130d2c (0028):  ori      v1,v1,0x11e418(1172504)
4158 * D/dalvikvm( 2377): 0x2f130d30 (002c):  beqz     v0,0x2f130df0 (L0x11f1f0)
4159 * D/dalvikvm( 2377): 0x2f130d34 (0030):  pref     0,0(v0)
4160 * D/dalvikvm( 2377): 0x2f130d38 (0034):  lw       a0,0(v0)
4161 * D/dalvikvm( 2377): 0x2f130d3c (0038):  bne      v1,a0,0x2f130d54 (L0x11f518)
4162 * D/dalvikvm( 2377): 0x2f130d40 (003c):  pref     0,8(v0)
4163 * D/dalvikvm( 2377): -------- dalvik offset: 0x000a @ +iget-object-quick (C) v3, v4, (#8)
4164 * D/dalvikvm( 2377): 0x2f130d44 (0040):  lw       a1,8(v0)
4165 * D/dalvikvm( 2377): -------- dalvik offset: 0x000a @ +invoke-virtual-quick (PI) v4
4166 * D/dalvikvm( 2377): 0x2f130d48 (0044):  sw       a1,12(s1)
4167 * D/dalvikvm( 2377): 0x2f130d4c (0048):  b        0x2f130e18 (L0x120150)
4168 * D/dalvikvm( 2377): 0x2f130d50 (004c):  lw       a0,116(s2)
4169 * D/dalvikvm( 2377): L0x11f518:
4170 * D/dalvikvm( 2377): 0x2f130d54 (0050):  lw       a0,16(s1)
4171 * D/dalvikvm( 2377): 0x2f130d58 (0054):  addiu    s4,s1,0xffffffe8(-24)
4172 * D/dalvikvm( 2377): 0x2f130d5c (0058):  beqz     a0,0x2f130e00 (L0x11f618)
4173 * D/dalvikvm( 2377): 0x2f130d60 (005c):  pref     1,0(s4)
4174 * D/dalvikvm( 2377): -------- BARRIER
4175 * D/dalvikvm( 2377): 0x2f130d64 (0060):  sw       a0,0(s4)
4176 * D/dalvikvm( 2377): 0x2f130d68 (0064):  addiu    s4,s4,0x0004(4)
4177 * D/dalvikvm( 2377): -------- BARRIER
4178 * D/dalvikvm( 2377): 0x2f130d6c (0068):  lui      s0,0x2d22(11554)
4179 * D/dalvikvm( 2377): 0x2f130d70 (006c):  ori      s0,s0,0x2d228464(757236836)
4180 * D/dalvikvm( 2377): 0x2f130d74 (0070):  lahi/lui a1,0x2f13(12051)
4181 * D/dalvikvm( 2377): 0x2f130d78 (0074):  lalo/ori a1,a1,0x2f130ddc(789777884)
4182 * D/dalvikvm( 2377): 0x2f130d7c (0078):  lahi/lui a2,0x2f13(12051)
4183 * D/dalvikvm( 2377): 0x2f130d80 (007c):  lalo/ori a2,a2,0x2f130e24(789777956)
4184 * D/dalvikvm( 2377): 0x2f130d84 (0080):  jal      0x2f12d1ec(789762540)
4185 * D/dalvikvm( 2377): 0x2f130d88 (0084):  nop
4186 * D/dalvikvm( 2377): 0x2f130d8c (0088):  b        0x2f130e24 (L0x11ed6c)
4187 * D/dalvikvm( 2377): 0x2f130d90 (008c):  nop
4188 * D/dalvikvm( 2377): 0x2f130d94 (0090):  b        0x2f130e04 (L0x11ffd0)
4189 * D/dalvikvm( 2377): 0x2f130d98 (0094):  lui      a0,0x2d22(11554)
4190 * D/dalvikvm( 2377): 0x2f130d9c (0098):  lw       a0,44(s4)
4191 * D/dalvikvm( 2377): 0x2f130da0 (009c):  bgtz     a1,0x2f130dc4 (L0x11fb98)
4192 * D/dalvikvm( 2377): 0x2f130da4 (00a0):  nop
4193 * D/dalvikvm( 2377): 0x2f130da8 (00a4):  lui      t9,0x2aba(10938)
4194 * D/dalvikvm( 2377): 0x2f130dac (00a8):  ori      t9,t9,0x2abae3f8(716891128)
4195 * D/dalvikvm( 2377): 0x2f130db0 (00ac):  move     a1,s2
4196 * D/dalvikvm( 2377): 0x2f130db4 (00b0):  jalr     ra,t9
4197 * D/dalvikvm( 2377): 0x2f130db8 (00b4):  nop
4198 * D/dalvikvm( 2377): 0x2f130dbc (00b8):  lw       gp,84(sp)
4199 * D/dalvikvm( 2377): 0x2f130dc0 (00bc):  move     a0,v0
4200 * D/dalvikvm( 2377): 0x2f130dc4 (00c0):  lahi/lui a1,0x2f13(12051)
4201 * D/dalvikvm( 2377): 0x2f130dc8 (00c4):  lalo/ori a1,a1,0x2f130ddc(789777884)
4202 * D/dalvikvm( 2377): 0x2f130dcc (00c8):  jal      0x2f12d0c4(789762244)
4203 * D/dalvikvm( 2377): 0x2f130dd0 (00cc):  nop
4204 * D/dalvikvm( 2377): 0x2f130dd4 (00d0):  b        0x2f130e04 (L0x11ffd0)
4205 * D/dalvikvm( 2377): 0x2f130dd8 (00d4):  lui      a0,0x2d22(11554)
4206 * D/dalvikvm( 2377): 0x2f130ddc (00d8): .align4
4207 * D/dalvikvm( 2377): L0x11ed2c:
4208 * D/dalvikvm( 2377): -------- dalvik offset: 0x000d @ move-result-object (PI) v3, (#0), (#0)
4209 * D/dalvikvm( 2377): 0x2f130ddc (00d8):  lw       a2,16(s2)
4210 * D/dalvikvm( 2377): 0x2f130de0 (00dc):  sw       a2,12(s1)
4211 * D/dalvikvm( 2377): 0x2f130de4 (00e0):  b        0x2f130e18 (L0x120150)
4212 * D/dalvikvm( 2377): 0x2f130de8 (00e4):  lw       a0,116(s2)
4213 * D/dalvikvm( 2377): 0x2f130dec (00e8):  undefined
4214 * D/dalvikvm( 2377): L0x11f1f0:
4215 * D/dalvikvm( 2377): -------- reconstruct dalvik PC : 0x2d228464 @ +0x000a
4216 * D/dalvikvm( 2377): 0x2f130df0 (00ec):  lui      a0,0x2d22(11554)
4217 * D/dalvikvm( 2377): 0x2f130df4 (00f0):  ori      a0,a0,0x2d228464(757236836)
4218 * D/dalvikvm( 2377): 0x2f130df8 (00f4):  b        0x2f130e0c (L0x120090)
4219 * D/dalvikvm( 2377): 0x2f130dfc (00f8):  lw       a1,108(s2)
4220 * D/dalvikvm( 2377): L0x11f618:
4221 * D/dalvikvm( 2377): -------- reconstruct dalvik PC : 0x2d228464 @ +0x000a
4222 * D/dalvikvm( 2377): 0x2f130e00 (00fc):  lui      a0,0x2d22(11554)
4223 * D/dalvikvm( 2377): 0x2f130e04 (0100):  ori      a0,a0,0x2d228464(757236836)
4224 * D/dalvikvm( 2377): Exception_Handling:
4225 * D/dalvikvm( 2377): 0x2f130e08 (0104):  lw       a1,108(s2)
4226 * D/dalvikvm( 2377): 0x2f130e0c (0108):  jalr     ra,a1
4227 * D/dalvikvm( 2377): 0x2f130e10 (010c):  nop
4228 * D/dalvikvm( 2377): 0x2f130e14 (0110): .align4
4229 * D/dalvikvm( 2377): L0x11edac:
4230 * D/dalvikvm( 2377): -------- chaining cell (hot): 0x000e
4231 * D/dalvikvm( 2377): 0x2f130e14 (0110):  lw       a0,116(s2)
4232 * D/dalvikvm( 2377): 0x2f130e18 (0114):  jalr     ra,a0
4233 * D/dalvikvm( 2377): 0x2f130e1c (0118):  nop
4234 * D/dalvikvm( 2377): 0x2f130e20 (011c):  data     0x2d22846c(757236844)
4235 * D/dalvikvm( 2377): 0x2f130e24 (0120): .align4
4236 * D/dalvikvm( 2377): L0x11ed6c:
4237 * D/dalvikvm( 2377): -------- chaining cell (predicted)
4238 * D/dalvikvm( 2377): 0x2f130e24 (0120):  data     0xe7fe(59390)
4239 * D/dalvikvm( 2377): 0x2f130e28 (0124):  data     0x0000(0)
4240 * D/dalvikvm( 2377): 0x2f130e2c (0128):  data     0x0000(0)
4241 * D/dalvikvm( 2377): 0x2f130e30 (012c):  data     0x0000(0)
4242 * D/dalvikvm( 2377): 0x2f130e34 (0130):  data     0x0000(0)
4243 */
4244static void genValidationForPredictedInline(CompilationUnit *cUnit, MIR *mir)
4245{
4246    CallsiteInfo *callsiteInfo = mir->meta.callsiteInfo;
4247    RegLocation rlThis = cUnit->regLocation[mir->dalvikInsn.vC];
4248
4249    rlThis = loadValue(cUnit, rlThis, kCoreReg);
4250    int regPredictedClass = dvmCompilerAllocTemp(cUnit);
4251    loadClassPointer(cUnit, regPredictedClass, (int) callsiteInfo);
4252    genNullCheck(cUnit, rlThis.sRegLow, rlThis.lowReg, mir->offset,
4253                 NULL);/* null object? */
4254    int regActualClass = dvmCompilerAllocTemp(cUnit);
4255    loadWordDisp(cUnit, rlThis.lowReg, offsetof(Object, clazz), regActualClass);
4256//    opRegReg(cUnit, kOpCmp, regPredictedClass, regActualClass);
4257    /*
4258     * Set the misPredBranchOver target so that it will be generated when the
4259     * code for the non-optimized invoke is generated.
4260     */
4261    callsiteInfo->misPredBranchOver = (LIR *) opCompareBranch(cUnit, kMipsBne, regPredictedClass, regActualClass);
4262}
4263
4264/* Extended MIR instructions like PHI */
4265static void handleExtendedMIR(CompilationUnit *cUnit, MIR *mir)
4266{
4267    int opOffset = mir->dalvikInsn.opcode - kMirOpFirst;
4268    char *msg = (char *)dvmCompilerNew(strlen(extendedMIROpNames[opOffset]) + 1,
4269                                       false);
4270    strcpy(msg, extendedMIROpNames[opOffset]);
4271    newLIR1(cUnit, kMipsPseudoExtended, (int) msg);
4272
4273    switch ((ExtendedMIROpcode)mir->dalvikInsn.opcode) {
4274        case kMirOpPhi: {
4275            char *ssaString = dvmCompilerGetSSAString(cUnit, mir->ssaRep);
4276            newLIR1(cUnit, kMipsPseudoSSARep, (int) ssaString);
4277            break;
4278        }
4279        case kMirOpNullNRangeUpCheck: {
4280            genHoistedChecksForCountUpLoop(cUnit, mir);
4281            break;
4282        }
4283        case kMirOpNullNRangeDownCheck: {
4284            genHoistedChecksForCountDownLoop(cUnit, mir);
4285            break;
4286        }
4287        case kMirOpLowerBound: {
4288            genHoistedLowerBoundCheck(cUnit, mir);
4289            break;
4290        }
4291        case kMirOpPunt: {
4292            genUnconditionalBranch(cUnit,
4293                                   (MipsLIR *) cUnit->loopAnalysis->branchToPCR);
4294            break;
4295        }
4296        case kMirOpCheckInlinePrediction: {
4297            genValidationForPredictedInline(cUnit, mir);
4298            break;
4299        }
4300        default:
4301            break;
4302    }
4303}
4304
4305/*
4306 * Create a PC-reconstruction cell for the starting offset of this trace.
4307 * Since the PCR cell is placed near the end of the compiled code which is
4308 * usually out of range for a conditional branch, we put two branches (one
4309 * branch over to the loop body and one layover branch to the actual PCR) at the
4310 * end of the entry block.
4311 */
4312static void setupLoopEntryBlock(CompilationUnit *cUnit, BasicBlock *entry,
4313                                MipsLIR *bodyLabel)
4314{
4315    /* Set up the place holder to reconstruct this Dalvik PC */
4316    MipsLIR *pcrLabel = (MipsLIR *) dvmCompilerNew(sizeof(MipsLIR), true);
4317    pcrLabel->opcode = kMipsPseudoPCReconstructionCell;
4318    pcrLabel->operands[0] =
4319        (int) (cUnit->method->insns + entry->startOffset);
4320    pcrLabel->operands[1] = entry->startOffset;
4321    /* Insert the place holder to the growable list */
4322    dvmInsertGrowableList(&cUnit->pcReconstructionList, (intptr_t) pcrLabel);
4323
4324    /*
4325     * Next, create two branches - one branch over to the loop body and the
4326     * other branch to the PCR cell to punt.
4327     */
4328    MipsLIR *branchToBody = (MipsLIR *) dvmCompilerNew(sizeof(MipsLIR), true);
4329    branchToBody->opcode = kMipsB;
4330    branchToBody->generic.target = (LIR *) bodyLabel;
4331    setupResourceMasks(branchToBody);
4332    cUnit->loopAnalysis->branchToBody = (LIR *) branchToBody;
4333
4334    MipsLIR *branchToPCR = (MipsLIR *) dvmCompilerNew(sizeof(MipsLIR), true);
4335    branchToPCR->opcode = kMipsB;
4336    branchToPCR->generic.target = (LIR *) pcrLabel;
4337    setupResourceMasks(branchToPCR);
4338    cUnit->loopAnalysis->branchToPCR = (LIR *) branchToPCR;
4339}
4340
4341#if defined(WITH_SELF_VERIFICATION)
4342static bool selfVerificationPuntOps(MIR *mir)
4343{
4344assert(0); /* MIPSTODO port selfVerificationPuntOps() */
4345    DecodedInstruction *decInsn = &mir->dalvikInsn;
4346
4347    /*
4348     * All opcodes that can throw exceptions and use the
4349     * TEMPLATE_THROW_EXCEPTION_COMMON template should be excluded in the trace
4350     * under self-verification mode.
4351     */
4352    switch (decInsn->opcode) {
4353        case OP_MONITOR_ENTER:
4354        case OP_MONITOR_EXIT:
4355        case OP_NEW_INSTANCE:
4356        case OP_NEW_INSTANCE_JUMBO:
4357        case OP_NEW_ARRAY:
4358        case OP_NEW_ARRAY_JUMBO:
4359        case OP_CHECK_CAST:
4360        case OP_CHECK_CAST_JUMBO:
4361        case OP_MOVE_EXCEPTION:
4362        case OP_FILL_ARRAY_DATA:
4363        case OP_EXECUTE_INLINE:
4364        case OP_EXECUTE_INLINE_RANGE:
4365            return true;
4366        default:
4367            return false;
4368    }
4369}
4370#endif
4371
4372void dvmCompilerMIR2LIR(CompilationUnit *cUnit)
4373{
4374    /* Used to hold the labels of each block */
4375    MipsLIR *labelList =
4376        (MipsLIR *) dvmCompilerNew(sizeof(MipsLIR) * cUnit->numBlocks, true);
4377    MipsLIR *headLIR = NULL;
4378    GrowableList chainingListByType[kChainingCellGap];
4379    int i;
4380
4381    /*
4382     * Initialize various types chaining lists.
4383     */
4384    for (i = 0; i < kChainingCellGap; i++) {
4385        dvmInitGrowableList(&chainingListByType[i], 2);
4386    }
4387
4388    /* Clear the visited flag for each block */
4389    dvmCompilerDataFlowAnalysisDispatcher(cUnit, dvmCompilerClearVisitedFlag,
4390                                          kAllNodes, false /* isIterative */);
4391
4392    GrowableListIterator iterator;
4393    dvmGrowableListIteratorInit(&cUnit->blockList, &iterator);
4394
4395    /* Traces start with a profiling entry point.  Generate it here */
4396    cUnit->profileCodeSize = genTraceProfileEntry(cUnit);
4397
4398    /* Handle the content in each basic block */
4399    for (i = 0; ; i++) {
4400        MIR *mir;
4401        BasicBlock *bb = (BasicBlock *) dvmGrowableListIteratorNext(&iterator);
4402        if (bb == NULL) break;
4403        if (bb->visited == true) continue;
4404
4405        labelList[i].operands[0] = bb->startOffset;
4406
4407        if (bb->blockType >= kChainingCellGap) {
4408            if (bb->isFallThroughFromInvoke == true) {
4409                /* Align this block first since it is a return chaining cell */
4410                newLIR0(cUnit, kMipsPseudoPseudoAlign4);
4411            }
4412            /*
4413             * Append the label pseudo LIR first. Chaining cells will be handled
4414             * separately afterwards.
4415             */
4416            dvmCompilerAppendLIR(cUnit, (LIR *) &labelList[i]);
4417        }
4418
4419        if (bb->blockType == kEntryBlock) {
4420            labelList[i].opcode = kMipsPseudoEntryBlock;
4421            if (bb->firstMIRInsn == NULL) {
4422                continue;
4423            } else {
4424              setupLoopEntryBlock(cUnit, bb,
4425                                  &labelList[bb->fallThrough->id]);
4426            }
4427        } else if (bb->blockType == kExitBlock) {
4428            labelList[i].opcode = kMipsPseudoExitBlock;
4429            goto gen_fallthrough;
4430        } else if (bb->blockType == kDalvikByteCode) {
4431            if (bb->hidden == true) continue;
4432            labelList[i].opcode = kMipsPseudoNormalBlockLabel;
4433            /* Reset the register state */
4434            dvmCompilerResetRegPool(cUnit);
4435            dvmCompilerClobberAllRegs(cUnit);
4436            dvmCompilerResetNullCheck(cUnit);
4437        } else {
4438            switch (bb->blockType) {
4439                case kChainingCellNormal:
4440                    labelList[i].opcode = kMipsPseudoChainingCellNormal;
4441                    /* handle the codegen later */
4442                    dvmInsertGrowableList(
4443                        &chainingListByType[kChainingCellNormal], i);
4444                    break;
4445                case kChainingCellInvokeSingleton:
4446                    labelList[i].opcode =
4447                        kMipsPseudoChainingCellInvokeSingleton;
4448                    labelList[i].operands[0] =
4449                        (int) bb->containingMethod;
4450                    /* handle the codegen later */
4451                    dvmInsertGrowableList(
4452                        &chainingListByType[kChainingCellInvokeSingleton], i);
4453                    break;
4454                case kChainingCellInvokePredicted:
4455                    labelList[i].opcode =
4456                        kMipsPseudoChainingCellInvokePredicted;
4457                    /*
4458                     * Move the cached method pointer from operand 1 to 0.
4459                     * Operand 0 was clobbered earlier in this routine to store
4460                     * the block starting offset, which is not applicable to
4461                     * predicted chaining cell.
4462                     */
4463                    labelList[i].operands[0] = labelList[i].operands[1];
4464                    /* handle the codegen later */
4465                    dvmInsertGrowableList(
4466                        &chainingListByType[kChainingCellInvokePredicted], i);
4467                    break;
4468                case kChainingCellHot:
4469                    labelList[i].opcode =
4470                        kMipsPseudoChainingCellHot;
4471                    /* handle the codegen later */
4472                    dvmInsertGrowableList(
4473                        &chainingListByType[kChainingCellHot], i);
4474                    break;
4475                case kPCReconstruction:
4476                    /* Make sure exception handling block is next */
4477                    labelList[i].opcode =
4478                        kMipsPseudoPCReconstructionBlockLabel;
4479                    handlePCReconstruction(cUnit,
4480                                           &labelList[cUnit->puntBlock->id]);
4481                    break;
4482                case kExceptionHandling:
4483                    labelList[i].opcode = kMipsPseudoEHBlockLabel;
4484                    if (cUnit->pcReconstructionList.numUsed) {
4485                        loadWordDisp(cUnit, rSELF, offsetof(Thread,
4486                                     jitToInterpEntries.dvmJitToInterpPunt),
4487                                     r_A1);
4488                        opReg(cUnit, kOpBlx, r_A1);
4489                    }
4490                    break;
4491                case kChainingCellBackwardBranch:
4492                    labelList[i].opcode =
4493                        kMipsPseudoChainingCellBackwardBranch;
4494                    /* handle the codegen later */
4495                    dvmInsertGrowableList(
4496                        &chainingListByType[kChainingCellBackwardBranch],
4497                        i);
4498                    break;
4499                default:
4500                    break;
4501            }
4502            continue;
4503        }
4504
4505        /*
4506         * Try to build a longer optimization unit. Currently if the previous
4507         * block ends with a goto, we continue adding instructions and don't
4508         * reset the register allocation pool.
4509         */
4510        for (BasicBlock *nextBB = bb; nextBB != NULL; nextBB = cUnit->nextCodegenBlock) {
4511            bb = nextBB;
4512            bb->visited = true;
4513            cUnit->nextCodegenBlock = NULL;
4514
4515            for (mir = bb->firstMIRInsn; mir; mir = mir->next) {
4516
4517                dvmCompilerResetRegPool(cUnit);
4518                if (gDvmJit.disableOpt & (1 << kTrackLiveTemps)) {
4519                    dvmCompilerClobberAllRegs(cUnit);
4520                }
4521
4522                if (gDvmJit.disableOpt & (1 << kSuppressLoads)) {
4523                    dvmCompilerResetDefTracking(cUnit);
4524                }
4525
4526                if ((int)mir->dalvikInsn.opcode >= (int)kMirOpFirst) {
4527                    handleExtendedMIR(cUnit, mir);
4528                    continue;
4529                }
4530
4531                Opcode dalvikOpcode = mir->dalvikInsn.opcode;
4532                InstructionFormat dalvikFormat =
4533                    dexGetFormatFromOpcode(dalvikOpcode);
4534                const char *note;
4535                if (mir->OptimizationFlags & MIR_INLINED) {
4536                    note = " (I)";
4537                } else if (mir->OptimizationFlags & MIR_INLINED_PRED) {
4538                    note = " (PI)";
4539                } else if (mir->OptimizationFlags & MIR_CALLEE) {
4540                    note = " (C)";
4541                } else {
4542                    note = NULL;
4543                }
4544
4545                MipsLIR *boundaryLIR =
4546                    newLIR2(cUnit, kMipsPseudoDalvikByteCodeBoundary,
4547                            mir->offset,
4548                            (int) dvmCompilerGetDalvikDisassembly(&mir->dalvikInsn,
4549                                                                  note));
4550                if (mir->ssaRep) {
4551                    char *ssaString = dvmCompilerGetSSAString(cUnit, mir->ssaRep);
4552                    newLIR1(cUnit, kMipsPseudoSSARep, (int) ssaString);
4553                }
4554
4555                /* Remember the first LIR for this block */
4556                if (headLIR == NULL) {
4557                    headLIR = boundaryLIR;
4558                    /* Set the first boundaryLIR as a scheduling barrier */
4559                    headLIR->defMask = ENCODE_ALL;
4560                }
4561
4562                bool notHandled;
4563                /*
4564                 * Debugging: screen the opcode first to see if it is in the
4565                 * do[-not]-compile list
4566                 */
4567                bool singleStepMe = SINGLE_STEP_OP(dalvikOpcode);
4568#if defined(WITH_SELF_VERIFICATION)
4569              if (singleStepMe == false) {
4570                  singleStepMe = selfVerificationPuntOps(mir);
4571              }
4572#endif
4573                if (singleStepMe || cUnit->allSingleStep) {
4574                    notHandled = false;
4575                    genInterpSingleStep(cUnit, mir);
4576                } else {
4577                    opcodeCoverage[dalvikOpcode]++;
4578                    switch (dalvikFormat) {
4579                        case kFmt10t:
4580                        case kFmt20t:
4581                        case kFmt30t:
4582                            notHandled = handleFmt10t_Fmt20t_Fmt30t(cUnit,
4583                                      mir, bb, labelList);
4584                            break;
4585                        case kFmt10x:
4586                            notHandled = handleFmt10x(cUnit, mir);
4587                            break;
4588                        case kFmt11n:
4589                        case kFmt31i:
4590                            notHandled = handleFmt11n_Fmt31i(cUnit, mir);
4591                            break;
4592                        case kFmt11x:
4593                            notHandled = handleFmt11x(cUnit, mir);
4594                            break;
4595                        case kFmt12x:
4596                            notHandled = handleFmt12x(cUnit, mir);
4597                            break;
4598                        case kFmt20bc:
4599                        case kFmt40sc:
4600                            notHandled = handleFmt20bc_Fmt40sc(cUnit, mir);
4601                            break;
4602                        case kFmt21c:
4603                        case kFmt31c:
4604                        case kFmt41c:
4605                            notHandled = handleFmt21c_Fmt31c_Fmt41c(cUnit, mir);
4606                            break;
4607                        case kFmt21h:
4608                            notHandled = handleFmt21h(cUnit, mir);
4609                            break;
4610                        case kFmt21s:
4611                            notHandled = handleFmt21s(cUnit, mir);
4612                            break;
4613                        case kFmt21t:
4614                            notHandled = handleFmt21t(cUnit, mir, bb,
4615                                                      labelList);
4616                            break;
4617                        case kFmt22b:
4618                        case kFmt22s:
4619                            notHandled = handleFmt22b_Fmt22s(cUnit, mir);
4620                            break;
4621                        case kFmt22c:
4622                        case kFmt52c:
4623                            notHandled = handleFmt22c_Fmt52c(cUnit, mir);
4624                            break;
4625                        case kFmt22cs:
4626                            notHandled = handleFmt22cs(cUnit, mir);
4627                            break;
4628                        case kFmt22t:
4629                            notHandled = handleFmt22t(cUnit, mir, bb,
4630                                                      labelList);
4631                            break;
4632                        case kFmt22x:
4633                        case kFmt32x:
4634                            notHandled = handleFmt22x_Fmt32x(cUnit, mir);
4635                            break;
4636                        case kFmt23x:
4637                            notHandled = handleFmt23x(cUnit, mir);
4638                            break;
4639                        case kFmt31t:
4640                            notHandled = handleFmt31t(cUnit, mir);
4641                            break;
4642                        case kFmt3rc:
4643                        case kFmt35c:
4644                        case kFmt5rc:
4645                            notHandled = handleFmt35c_3rc_5rc(cUnit, mir, bb,
4646                                                          labelList);
4647                            break;
4648                        case kFmt3rms:
4649                        case kFmt35ms:
4650                            notHandled = handleFmt35ms_3rms(cUnit, mir,bb,
4651                                                            labelList);
4652                            break;
4653                        case kFmt35mi:
4654                        case kFmt3rmi:
4655                            notHandled = handleExecuteInline(cUnit, mir);
4656                            break;
4657                        case kFmt51l:
4658                            notHandled = handleFmt51l(cUnit, mir);
4659                            break;
4660                        default:
4661                            notHandled = true;
4662                            break;
4663                    }
4664                }
4665                if (notHandled) {
4666                    LOGE("%#06x: Opcode %#x (%s) / Fmt %d not handled",
4667                         mir->offset,
4668                         dalvikOpcode, dexGetOpcodeName(dalvikOpcode),
4669                         dalvikFormat);
4670                    dvmCompilerAbort(cUnit);
4671                    break;
4672                }
4673            }
4674        }
4675
4676        if (bb->blockType == kEntryBlock) {
4677            dvmCompilerAppendLIR(cUnit,
4678                                 (LIR *) cUnit->loopAnalysis->branchToBody);
4679            dvmCompilerAppendLIR(cUnit,
4680                                 (LIR *) cUnit->loopAnalysis->branchToPCR);
4681        }
4682
4683        if (headLIR) {
4684            /*
4685             * Eliminate redundant loads/stores and delay stores into later
4686             * slots
4687             */
4688            dvmCompilerApplyLocalOptimizations(cUnit, (LIR *) headLIR,
4689                                               cUnit->lastLIRInsn);
4690            /* Reset headLIR which is also the optimization boundary */
4691            headLIR = NULL;
4692        }
4693
4694gen_fallthrough:
4695        /*
4696         * Check if the block is terminated due to trace length constraint -
4697         * insert an unconditional branch to the chaining cell.
4698         */
4699        if (bb->needFallThroughBranch) {
4700            genUnconditionalBranch(cUnit, &labelList[bb->fallThrough->id]);
4701        }
4702    }
4703
4704    /* Handle the chaining cells in predefined order */
4705    for (i = 0; i < kChainingCellGap; i++) {
4706        size_t j;
4707        int *blockIdList = (int *) chainingListByType[i].elemList;
4708
4709        cUnit->numChainingCells[i] = chainingListByType[i].numUsed;
4710
4711        /* No chaining cells of this type */
4712        if (cUnit->numChainingCells[i] == 0)
4713            continue;
4714
4715        /* Record the first LIR for a new type of chaining cell */
4716        cUnit->firstChainingLIR[i] = (LIR *) &labelList[blockIdList[0]];
4717
4718        for (j = 0; j < chainingListByType[i].numUsed; j++) {
4719            int blockId = blockIdList[j];
4720            BasicBlock *chainingBlock =
4721                (BasicBlock *) dvmGrowableListGetElement(&cUnit->blockList,
4722                                                         blockId);
4723
4724            /* Align this chaining cell first */
4725            newLIR0(cUnit, kMipsPseudoPseudoAlign4);
4726
4727            /* Insert the pseudo chaining instruction */
4728            dvmCompilerAppendLIR(cUnit, (LIR *) &labelList[blockId]);
4729
4730
4731            switch (chainingBlock->blockType) {
4732                case kChainingCellNormal:
4733                    handleNormalChainingCell(cUnit, chainingBlock->startOffset);
4734                    break;
4735                case kChainingCellInvokeSingleton:
4736                    handleInvokeSingletonChainingCell(cUnit,
4737                        chainingBlock->containingMethod);
4738                    break;
4739                case kChainingCellInvokePredicted:
4740                    handleInvokePredictedChainingCell(cUnit);
4741                    break;
4742                case kChainingCellHot:
4743                    handleHotChainingCell(cUnit, chainingBlock->startOffset);
4744                    break;
4745                case kChainingCellBackwardBranch:
4746                    handleBackwardBranchChainingCell(cUnit,
4747                        chainingBlock->startOffset);
4748                    break;
4749                default:
4750                    LOGE("Bad blocktype %d", chainingBlock->blockType);
4751                    dvmCompilerAbort(cUnit);
4752            }
4753        }
4754    }
4755
4756    /* Mark the bottom of chaining cells */
4757    cUnit->chainingCellBottom = (LIR *) newLIR0(cUnit, kMipsChainingCellBottom);
4758
4759    /*
4760     * Generate the branch to the dvmJitToInterpNoChain entry point at the end
4761     * of all chaining cells for the overflow cases.
4762     */
4763    if (cUnit->switchOverflowPad) {
4764        loadConstant(cUnit, r_A0, (int) cUnit->switchOverflowPad);
4765        loadWordDisp(cUnit, rSELF, offsetof(Thread,
4766                     jitToInterpEntries.dvmJitToInterpNoChain), r_A2);
4767        opRegReg(cUnit, kOpAdd, r_A1, r_A1);
4768        opRegRegReg(cUnit, kOpAdd, r4PC, r_A0, r_A1);
4769#if defined(WITH_JIT_TUNING)
4770        loadConstant(cUnit, r_A0, kSwitchOverflow);
4771#endif
4772        opReg(cUnit, kOpBlx, r_A2);
4773    }
4774
4775    dvmCompilerApplyGlobalOptimizations(cUnit);
4776
4777#if defined(WITH_SELF_VERIFICATION)
4778    selfVerificationBranchInsertPass(cUnit);
4779#endif
4780}
4781
4782/*
4783 * Accept the work and start compiling.  Returns true if compilation
4784 * is attempted.
4785 */
4786bool dvmCompilerDoWork(CompilerWorkOrder *work)
4787{
4788    JitTraceDescription *desc;
4789    bool isCompile;
4790    bool success = true;
4791
4792    if (gDvmJit.codeCacheFull) {
4793        return false;
4794    }
4795
4796    switch (work->kind) {
4797        case kWorkOrderTrace:
4798            isCompile = true;
4799            /* Start compilation with maximally allowed trace length */
4800            desc = (JitTraceDescription *)work->info;
4801            success = dvmCompileTrace(desc, JIT_MAX_TRACE_LEN, &work->result,
4802                                        work->bailPtr, 0 /* no hints */);
4803            break;
4804        case kWorkOrderTraceDebug: {
4805            bool oldPrintMe = gDvmJit.printMe;
4806            gDvmJit.printMe = true;
4807            isCompile = true;
4808            /* Start compilation with maximally allowed trace length */
4809            desc = (JitTraceDescription *)work->info;
4810            success = dvmCompileTrace(desc, JIT_MAX_TRACE_LEN, &work->result,
4811                                        work->bailPtr, 0 /* no hints */);
4812            gDvmJit.printMe = oldPrintMe;
4813            break;
4814        }
4815        case kWorkOrderProfileMode:
4816            dvmJitChangeProfileMode((TraceProfilingModes)(int)work->info);
4817            isCompile = false;
4818            break;
4819        default:
4820            isCompile = false;
4821            LOGE("Jit: unknown work order type");
4822            assert(0);  // Bail if debug build, discard otherwise
4823    }
4824    if (!success)
4825        work->result.codeAddress = NULL;
4826    return isCompile;
4827}
4828
4829/* Architectural-specific debugging helpers go here */
4830void dvmCompilerArchDump(void)
4831{
4832    /* Print compiled opcode in this VM instance */
4833    int i, start, streak;
4834    char buf[1024];
4835
4836    streak = i = 0;
4837    buf[0] = 0;
4838    while (opcodeCoverage[i] == 0 && i < 256) {
4839        i++;
4840    }
4841    if (i == 256) {
4842        return;
4843    }
4844    for (start = i++, streak = 1; i < 256; i++) {
4845        if (opcodeCoverage[i]) {
4846            streak++;
4847        } else {
4848            if (streak == 1) {
4849                sprintf(buf+strlen(buf), "%x,", start);
4850            } else {
4851                sprintf(buf+strlen(buf), "%x-%x,", start, start + streak - 1);
4852            }
4853            streak = 0;
4854            while (opcodeCoverage[i] == 0 && i < 256) {
4855                i++;
4856            }
4857            if (i < 256) {
4858                streak = 1;
4859                start = i;
4860            }
4861        }
4862    }
4863    if (streak) {
4864        if (streak == 1) {
4865            sprintf(buf+strlen(buf), "%x", start);
4866        } else {
4867            sprintf(buf+strlen(buf), "%x-%x", start, start + streak - 1);
4868        }
4869    }
4870    if (strlen(buf)) {
4871        LOGD("dalvik.vm.jit.op = %s", buf);
4872    }
4873}
4874
4875/* Common initialization routine for an architecture family */
4876bool dvmCompilerArchInit()
4877{
4878    int i;
4879
4880    for (i = 0; i < kMipsLast; i++) {
4881        if (EncodingMap[i].opcode != i) {
4882            LOGE("Encoding order for %s is wrong: expecting %d, seeing %d",
4883                 EncodingMap[i].name, i, EncodingMap[i].opcode);
4884            dvmAbort();  // OK to dvmAbort - build error
4885        }
4886    }
4887
4888    return dvmCompilerArchVariantInit();
4889}
4890
4891void *dvmCompilerGetInterpretTemplate()
4892{
4893      return (void*) ((int)gDvmJit.codeCache +
4894                      templateEntryOffsets[TEMPLATE_INTERPRET]);
4895}
4896
4897JitInstructionSetType dvmCompilerGetInterpretTemplateSet()
4898{
4899    return DALVIK_JIT_MIPS;
4900}
4901
4902/* Needed by the Assembler */
4903void dvmCompilerSetupResourceMasks(MipsLIR *lir)
4904{
4905    setupResourceMasks(lir);
4906}
4907
4908/* Needed by the ld/st optmizatons */
4909MipsLIR* dvmCompilerRegCopyNoInsert(CompilationUnit *cUnit, int rDest, int rSrc)
4910{
4911    return genRegCopyNoInsert(cUnit, rDest, rSrc);
4912}
4913
4914/* Needed by the register allocator */
4915MipsLIR* dvmCompilerRegCopy(CompilationUnit *cUnit, int rDest, int rSrc)
4916{
4917    return genRegCopy(cUnit, rDest, rSrc);
4918}
4919
4920/* Needed by the register allocator */
4921void dvmCompilerRegCopyWide(CompilationUnit *cUnit, int destLo, int destHi,
4922                            int srcLo, int srcHi)
4923{
4924    genRegCopyWide(cUnit, destLo, destHi, srcLo, srcHi);
4925}
4926
4927void dvmCompilerFlushRegImpl(CompilationUnit *cUnit, int rBase,
4928                             int displacement, int rSrc, OpSize size)
4929{
4930    storeBaseDisp(cUnit, rBase, displacement, rSrc, size);
4931}
4932
4933void dvmCompilerFlushRegWideImpl(CompilationUnit *cUnit, int rBase,
4934                                 int displacement, int rSrcLo, int rSrcHi)
4935{
4936    storeBaseDispWide(cUnit, rBase, displacement, rSrcLo, rSrcHi);
4937}
4938