1ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng /* 2ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Compare two 64-bit values. Puts 0, 1, or -1 into the destination 3ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * register based on the results of the comparison. 4ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * 5ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * We load the full values with LDM, but in practice many values could 6ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * be resolved by only looking at the high word. This could be made 7ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * faster or slower by splitting the LDM into a pair of LDRs. 8ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * 9ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * If we just wanted to set condition flags, we could do this: 10ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * subs ip, r0, r2 11ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * sbcs ip, r1, r3 12ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * subeqs ip, r0, r2 13ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * Leaving { <0, 0, >0 } in ip. However, we have to set it to a specific 14ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * integer value, which we can do with 2 conditional mov/mvn instructions 15ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * (set 1, set -1; if they're equal we already have 0 in ip), giving 16ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * us a constant 5-cycle path plus a branch at the end to the 17ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * instruction epilogue code. The multi-compare approach below needs 18ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * 2 or 3 cycles + branch if the high word doesn't match, 6 + branch 19ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng * in the worst case (the 64-bit values are equal). 20ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng */ 21ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng /* cmp-long vAA, vBB, vCC */ 22ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng cmp r1, r3 @ compare (vBB+1, vCC+1) 23ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng blt .L${opcode}_less @ signed compare on high part 24ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bgt .L${opcode}_greater 25ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng subs r0, r0, r2 @ r0<- r0 - r2 26ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bxeq lr 27ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bhi .L${opcode}_greater @ unsigned compare on low part 28ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng.L${opcode}_less: 29ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mvn r0, #0 @ r0<- -1 30ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bx lr 31ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng.L${opcode}_greater: 32ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng mov r0, #1 @ r0<- 1 33ba4fc8bfc1bccae048403bd1cea3b869dca61dd7Ben Cheng bx lr 34