TEMPLATE_CMP_LONG.S revision a8b91c52fd8a90b784835dfe1f8898035266c4dd 
1%verify "endianess"
2    /*
3     * Compare two 64-bit values
4     *    x = y     return  0
5     *    x < y     return -1
6     *    x > y     return  1
7     *
8     * I think I can improve on the ARM code by the following observation
9     *    slt   t0,  x.hi, y.hi;        # (x.hi < y.hi) ? 1:0
10     *    sgt   t1,  x.hi, y.hi;        # (y.hi > x.hi) ? 1:0
11     *    subu  v0, t0, t1              # v0= -1:1:0 for [ < > = ]
12     *
13     * This code assumes the register pair ordering will depend on endianess (a1:a0 or a0:a1).
14     *    a1:a0 => vBB
15     *    a3:a2 => vCC
16     */
17    /* cmp-long vAA, vBB, vCC */
18    slt    t0, rARG1, rARG3             # compare hi
19    sgt    t1, rARG1, rARG3
20    subu   v0, t1, t0                   # v0<- (-1,1,0)
21    bnez   v0, .L${opcode}_finish
22                                        # at this point x.hi==y.hi
23    sltu   t0, rARG0, rARG2             # compare lo
24    sgtu   t1, rARG0, rARG2
25    subu   v0, t1, t0                   # v0<- (-1,1,0) for [< > =]
26.L${opcode}_finish:
27    RETURN
28