CompilerTemplateAsm-ia32.S revision 5dfcc78af479937ba8dafceefd9b1931a88dfaaf 
1/*
2 * This file was generated automatically by gen-template.py for 'ia32'.
3 *
4 * --> DO NOT EDIT <--
5 */
6
7/* File: ia32/header.S */
8/*
9 * Copyright (C) 2010 The Android Open Source Project
10 *
11 * Licensed under the Apache License, Version 2.0 (the "License");
12 * you may not use this file except in compliance with the License.
13 * You may obtain a copy of the License at
14 *
15 *      http://www.apache.org/licenses/LICENSE-2.0
16 *
17 * Unless required by applicable law or agreed to in writing, software
18 * distributed under the License is distributed on an "AS IS" BASIS,
19 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
20 * See the License for the specific language governing permissions and
21 * limitations under the License.
22 */
23
24#if defined(WITH_JIT)
25
26/* Subset of defines from mterp/x86/header.S */
27#define rSELF (%ebp)
28#define rPC   %esi
29#define rFP   %edi
30#define rINST %ebx
31
32/*
33 * This is a #include, not a %include, because we want the C pre-processor
34 * to expand the macros into assembler assignment statements.
35 */
36#include "../../../mterp/common/asm-constants.h"
37
38/* File: ia32/platform.S */
39/*
40 * ===========================================================================
41 *  CPU-version-specific defines and utility
42 * ===========================================================================
43 */
44
45
46
47
48    .global dvmCompilerTemplateStart
49    .type   dvmCompilerTemplateStart, %function
50    .section .data.rel.ro
51
52dvmCompilerTemplateStart:
53
54/* ------------------------------ */
55    .balign 4
56    .global dvmCompiler_TEMPLATE_INTERPRET
57dvmCompiler_TEMPLATE_INTERPRET:
58/* File: ia32/TEMPLATE_INTERPRET.S */
59    /*
60     * This handler is a bit odd - it may be called via chaining or
61     * from static code and is expected to cause control to flow
62     * to the interpreter.  The problem is where to find the Dalvik
63     * PC of the next instruction.  When called via chaining, the dPC
64     * will be located at *rp.  When called from static code, rPC is
65     * valid and rp is a real return pointer (that should be ignored).
66     * The Arm target deals with this by using the link register as
67     * a flag.  If it is zero, we know we were called from static code.
68     * If non-zero, it points to the chain cell containing dPC.
69     * For x86, we'll infer the source by looking where rp points.
70     * If it points to anywhere within the code cache, we'll assume
71     * we got here via chaining.  Otherwise, we'll assume rPC is valid.
72     *
73     * On entry:
74     *    (TOS)<- return pointer or pointer to dPC
75     */
76
77/*
78 * FIXME - this won't work as-is.  The cache boundaries are not
79 * set up until later.  Perhaps rething this whole thing.  Do we
80 * really need an interpret teplate?
81 */
82
83
84     movl   rSELF,%ecx
85     movl   $.LinterpPunt,%edx
86     pop    %eax
87     /*cmpl   %eax,offThread_jitCacheEnd(%ecx)*/
88     ja     1f
89     /*cmpl   %eax,offThread_jitCacheStart(%ecx)*/
90     jb     1f
91     movl   %eax,rPC
921:
93     jmp    *(%edx)
94
95.LinterpPunt:
96    .long   dvmJitToInterpPunt
97
98    .size   dvmCompilerTemplateStart, .-dvmCompilerTemplateStart
99/* File: ia32/footer.S */
100/*
101 * ===========================================================================
102 *  Common subroutines and data
103 * ===========================================================================
104 */
105
106    .section .data.rel.ro
107    .align  4
108
109    .global dmvCompilerTemplateEnd
110dmvCompilerTemplateEnd:
111
112#endif /* WITH_JIT */
113
114