OP_CMP_LONG.S revision a8b91c52fd8a90b784835dfe1f8898035266c4dd 
1%verify "executed"
2%verify "basic lt, gt, eq"
3%verify "hi equal, lo <=>"
4%verify "lo equal, hi <=>"
5    /*
6     * Compare two 64-bit values
7     *    x = y     return  0
8     *    x < y     return -1
9     *    x > y     return  1
10     *
11     * I think I can improve on the ARM code by the following observation
12     *    slt   t0,  x.hi, y.hi;	# (x.hi < y.hi) ? 1:0
13     *    sgt   t1,  x.hi, y.hi;	# (y.hi > x.hi) ? 1:0
14     *    subu  v0, t0, t1              # v0= -1:1:0 for [ < > = ]
15     */
16    /* cmp-long vAA, vBB, vCC */
17    FETCH(a0, 1)                           #  a0 <- CCBB
18    GET_OPA(rOBJ)                          #  rOBJ <- AA
19    and       a2, a0, 255                  #  a2 <- BB
20    srl       a3, a0, 8                    #  a3 <- CC
21    EAS2(a2, rFP, a2)                      #  a2 <- &fp[BB]
22    EAS2(a3, rFP, a3)                      #  a3 <- &fp[CC]
23    LOAD64(a0, a1, a2)                     #  a0/a1 <- vBB/vBB+1
24    LOAD64(a2, a3, a3)                     #  a2/a3 <- vCC/vCC+1
25
26    FETCH_ADVANCE_INST(2)                  #  advance rPC, load rINST
27    slt       t0, a1, a3                   #  compare hi
28    sgt       t1, a1, a3
29    subu      v0, t1, t0                   #  v0 <- (-1, 1, 0)
30    bnez      v0, .L${opcode}_finish
31    # at this point x.hi==y.hi
32    sltu      t0, a0, a2                   #  compare lo
33    sgtu      t1, a0, a2
34    subu      v0, t1, t0                   #  v0 <- (-1, 1, 0) for [< > =]
35
36.L${opcode}_finish:
37    SET_VREG(v0, rOBJ)                     #  vAA <- v0
38    GET_INST_OPCODE(t0)                    #  extract opcode from rINST
39    GOTO_OPCODE(t0)                        #  jump to next instruction
40
41