OP_SHL_LONG.S revision a8b91c52fd8a90b784835dfe1f8898035266c4dd 
1%verify "executed"
2    /*
3     * Long integer shift.  This is different from the generic 32/64-bit
4     * binary operations because vAA/vBB are 64-bit but vCC (the shift
5     * distance) is 32-bit.  Also, Dalvik requires us to mask off the low
6     * 6 bits of the shift distance.
7     */
8    /* shl-long vAA, vBB, vCC */
9    FETCH(a0, 1)                           #  a0 <- CCBB
10    GET_OPA(t2)                            #  t2 <- AA
11    and       a3, a0, 255                  #  a3 <- BB
12    srl       a0, a0, 8                    #  a0 <- CC
13    EAS2(a3, rFP, a3)                      #  a3 <- &fp[BB]
14    GET_VREG(a2, a0)                       #  a2 <- vCC
15    LOAD64(a0, a1, a3)                     #  a0/a1 <- vBB/vBB+1
16
17    EAS2(t2, rFP, t2)                      #  t2 <- &fp[AA]
18    FETCH_ADVANCE_INST(2)                  #  advance rPC, load rINST
19
20    sll     v0, a0, a2                     #  rlo<- alo << (shift&31)
21    not     v1, a2                         #  rhi<- 31-shift  (shift is 5b)
22    srl     a0, 1
23    srl     a0, v1                         #  alo<- alo >> (32-(shift&31))
24    sll     v1, a1, a2                     #  rhi<- ahi << (shift&31)
25    or      v1, a0                         #  rhi<- rhi | alo
26    andi    a2, 0x20                       #  shift< shift & 0x20
27    movn    v1, v0, a2                     #  rhi<- rlo (if shift&0x20)
28    movn    v0, zero, a2                   #  rlo<- 0  (if shift&0x20)
29
30    GET_INST_OPCODE(t0)                    #  extract opcode from rINST
31    STORE64(v0, v1, t2)                    #  vAA/vAA+1 <- a0/a1
32    GOTO_OPCODE(t0)                        #  jump to next instruction
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