binflop2addr.S revision a8b91c52fd8a90b784835dfe1f8898035266c4dd 
1%default {"preinstr":"", "chkzero":"0"}
2    /*
3     * Generic 32-bit "/2addr" binary operation.  Provide an "instr" and
4     * "instr_f" line
5     * that specifies an instruction that performs "result = a0 op a1".
6     * This could be an MIPS instruction or a function call.
7     * If "chkzero" is set to 1, we perform a divide-by-zero check on
8     * vCC (a1).  Useful for integer division and modulus.
9     *
10     * For: add-float/2addr, sub-float/2addr, mul-float/2addr,
11     * div-float/2addr, rem-float/2addr
12     */
13    /* binop/2addr vA, vB */
14    GET_OPA4(rOBJ)                         #  t1 <- A+
15    GET_OPB(a3)                            #  a3 <- B
16#ifdef SOFT_FLOAT
17    GET_VREG(a0, rOBJ)                     #  a0 <- vA
18    GET_VREG(a1, a3)                       #  a1 <- vB
19    .if $chkzero
20    # is second operand zero?
21    beqz      a1, common_errDivideByZero
22    .endif
23#else
24    GET_VREG_F(fa0, rOBJ)
25    GET_VREG_F(fa1, a3)
26    .if $chkzero
27    # is second operand zero?
28    li.s      ft0, 0
29    c.eq.s    fcc0, ft0, fa1
30    bc1t      fcc0, common_errDivideByZero
31    .endif
32#endif
33    FETCH_ADVANCE_INST(1)                  #  advance rPC, load rINST
34    $preinstr                              #  optional op
35#ifdef SOFT_FLOAT
36    $instr                                 #  result <- op, a0-a3 changed
37    SET_VREG(v0, rOBJ)                     #  vAA <- result
38#else
39    $instr_f
40    SET_VREG_F(fv0, rOBJ)                  #  vAA <- result
41#endif
42    GET_INST_OPCODE(t0)                    #  extract opcode from rINST
43    GOTO_OPCODE(t0)                        #  jump to next instruction
44    /* 10-13 instructions */
45
46