header.S revision 0c2dc522d0e120f346cf0a40c8cf0c93346131c2 
1/*
2 * Copyright (C) 2008 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16/*
17 * 32-bit x86 definitions and declarations.
18 */
19
20/*
21386 ABI general notes:
22
23Caller save set:
24   eax, edx, ecx, st(0)-st(7)
25Callee save set:
26   ebx, esi, edi, ebp
27Return regs:
28   32-bit in eax
29   64-bit in edx:eax (low-order 32 in eax)
30   fp on top of fp stack st(0)
31
32Parameters passed on stack, pushed right-to-left.  On entry to target, first
33parm is at 4(%esp).  Traditional entry code is:
34
35functEntry:
36    push    %ebp             # save old frame pointer
37    mov     %ebp,%esp        # establish new frame pointer
38    sub     FrameSize,%esp   # Allocate storage for spill, locals & outs
39
40Once past the prologue, arguments are referenced at ((argno + 2)*4)(%ebp)
41
42Stack must be 16-byte aligned to support SSE in native code.
43
44If we're not doing variable stack allocation (alloca), the frame pointer can be
45eliminated and all arg references adjusted to be esp relative.
46
47Mterp notes:
48
49Some key interpreter variables will be assigned to registers.  Note that each
50will also have an associated spill location (mostly useful for those assigned
51to callee save registers).
52
53  nick     reg   purpose
54  rPC      esi   interpreted program counter, used for fetching instructions
55  rFP      edi   interpreted frame pointer, used for accessing locals and args
56  rINSTw   bx    first 16-bit code of current instruction
57  rINSTbl  bl    opcode portion of instruction word
58  rINSTbh  bh    high byte of inst word, usually contains src/tgt reg names
59  rIBASE   edx   base of instruction handler table
60
61Notes:
62   o High order 16 bits of ebx must be zero on entry to handler
63   o rPC, rFP, rINSTw/rINSTbl valid on handler entry and exit
64   o eax and ecx are scratch, rINSTw/ebx sometimes scratch
65
66*/
67
68#define rSELF    8(%ebp)
69#define rPC      %esi
70#define rFP      %edi
71#define rINST    %ebx
72#define rINSTw   %bx
73#define rINSTbh  %bh
74#define rINSTbl  %bl
75#define rIBASE   %edx
76
77
78/* Frame diagram while executing dvmMterpStdRun, high to low addresses */
79#define IN_ARG0        (  8)
80#define CALLER_RP      (  4)
81#define PREV_FP        (  0)
82/* Spill offsets relative to %ebp */
83#define EDI_SPILL      ( -4)
84#define ESI_SPILL      ( -8)
85#define EBX_SPILL      (-12)
86#define rPC_SPILL      (-16)
87#define rFP_SPILL      (-20)
88#define rINST_SPILL    (-24)
89#define rIBASE_SPILL   (-28)
90#define TMP_SPILL1     (-32)
91#define TMP_SPILL2     (-36)
92#define TMP_SPILL3     (-20)
93#define LOCAL0_OFFSET  (-44)
94#define LOCAL1_OFFSET  (-48)
95#define LOCAL2_OFFSET  (-52)
96/* Out Arg offsets, relative to %esp */
97#define OUT_ARG4       ( 16)
98#define OUT_ARG3       ( 12)
99#define OUT_ARG2       (  8)
100#define OUT_ARG1       (  4)
101#define OUT_ARG0       (  0)  /* <- dvmMterpStdRun esp */
102#if defined(WITH_JIT)
103/* for spill region: increase size by 48 (to keep 16-byte alignment) */
104/* 76 + 48 = 124 */
105#define JIT_SPILL      (-56)
106#define FRAME_SIZE     124
107#else
108#define FRAME_SIZE     76
109#endif
110
111#define SPILL(reg) movl reg##,reg##_SPILL(%ebp)
112#define UNSPILL(reg) movl reg##_SPILL(%ebp),reg
113#define SPILL_TMP1(reg) movl reg,TMP_SPILL1(%ebp)
114#define UNSPILL_TMP1(reg) movl TMP_SPILL1(%ebp),reg
115#define SPILL_TMP2(reg) movl reg,TMP_SPILL2(%ebp)
116#define UNSPILL_TMP2(reg) movl TMP_SPILL2(%ebp),reg
117#define SPILL_TMP3(reg) movl reg,TMP_SPILL3(%ebp)
118#define UNSPILL_TMP3(reg) movl TMP_SPILL3(%ebp),reg
119
120#if defined(WITH_JIT)
121.macro GET_JIT_PROF_TABLE _self _reg
122    movl    offThread_pJitProfTable(\_self),\_reg
123.endm
124.macro GET_JIT_THRESHOLD _self _reg
125    movl    offThread_jitThreshold(\_self),\_reg
126.endm
127#endif
128
129/* save/restore the PC and/or FP from the self struct */
130.macro SAVE_PC_FP_TO_SELF _reg
131    movl     rSELF,\_reg
132    movl     rPC,offThread_pc(\_reg)
133    movl     rFP,offThread_curFrame(\_reg)
134.endm
135
136.macro LOAD_PC_FP_FROM_SELF
137    movl    rSELF,rFP
138    movl    offThread_pc(rFP),rPC
139    movl    offThread_curFrame(rFP),rFP
140.endm
141
142/* The interpreter assumes a properly aligned stack on entry, and
143 * will preserve 16-byte alignment.
144 */
145
146/*
147 * "export" the PC to the interpreted stack frame, f/b/o future exception
148 * objects.  Must be done *before* something throws.
149 *
150 * In C this is "SAVEAREA_FROM_FP(fp)->xtra.currentPc = pc", i.e.
151 * fp - sizeof(StackSaveArea) + offsetof(SaveArea, xtra.currentPc)
152 *
153 * It's okay to do this more than once.
154 */
155.macro EXPORT_PC
156    movl     rPC, (-sizeofStackSaveArea + offStackSaveArea_currentPc)(rFP)
157.endm
158
159.macro GET_PC
160    movl     (-sizeofStackSaveArea + offStackSaveArea_currentPc)(rFP), rPC
161.endm
162
163/*
164 * Given a frame pointer, find the stack save area.
165 *
166 * In C this is "((StackSaveArea*)(_fp) -1)".
167 */
168.macro SAVEAREA_FROM_FP _reg
169    leal    -sizeofStackSaveArea(rFP), \_reg
170.endm
171
172/*
173 * Fetch the next instruction from rPC into rINSTw.  Does not advance rPC.
174 */
175.macro FETCH_INST
176    movzwl    (rPC),rINST
177.endm
178
179/*
180 * Fetch the opcode byte and zero-extend it into _reg.  Must be used
181 * in conjunction with GOTO_NEXT_R
182 */
183.macro FETCH_INST_R _reg
184    movzbl    (rPC),\_reg
185.endm
186
187/*
188 * Fetch the opcode byte at _count words offset from rPC and zero-extend
189 * it into _reg.  Must be used in conjunction with GOTO_NEXT_R
190 */
191.macro FETCH_INST_OPCODE _count _reg
192    movzbl  \_count*2(rPC),\_reg
193.endm
194
195/*
196 * Fetch the nth instruction word from rPC into rINSTw.  Does not advance
197 * rPC, and _count is in words
198 */
199.macro FETCH_INST_WORD _count
200    movzwl  \_count*2(rPC),rINST
201.endm
202
203/*
204 * Fetch instruction word indexed (used for branching).
205 * Index is in instruction word units.
206 */
207.macro FETCH_INST_INDEXED _reg
208    movzwl  (rPC,\_reg,2),rINST
209.endm
210
211/*
212 * Advance rPC by instruction count
213 */
214.macro ADVANCE_PC _count
215    leal  2*\_count(rPC),rPC
216.endm
217
218/*
219 * Advance rPC by branch offset in register
220 */
221.macro ADVANCE_PC_INDEXED _reg
222    leal (rPC,\_reg,2),rPC
223.endm
224
225.macro GOTO_NEXT
226     movzx   rINSTbl,%eax
227     movzbl  rINSTbh,rINST
228     jmp     *(rIBASE,%eax,4)
229.endm
230
231   /*
232    * Version of GOTO_NEXT that assumes _reg preloaded with opcode.
233    * Should be paired with FETCH_INST_R
234    */
235.macro GOTO_NEXT_R _reg
236     movzbl  1(rPC),rINST
237     jmp     *(rIBASE,\_reg,4)
238.endm
239
240/*
241 * Get/set the 32-bit value from a Dalvik register.
242 */
243.macro GET_VREG_R _reg _vreg
244    movl     (rFP,\_vreg,4),\_reg
245.endm
246
247.macro SET_VREG _reg _vreg
248    movl     \_reg,(rFP,\_vreg,4)
249.endm
250
251.macro GET_VREG_WORD _reg _vreg _offset
252    movl     4*(\_offset)(rFP,\_vreg,4),\_reg
253.endm
254
255.macro SET_VREG_WORD _reg _vreg _offset
256    movl     \_reg,4*(\_offset)(rFP,\_vreg,4)
257.endm
258
259#define sReg0 LOCAL0_OFFSET(%ebp)
260#define sReg1 LOCAL1_OFFSET(%ebp)
261#define sReg2 LOCAL2_OFFSET(%ebp)
262
263   /*
264    * x86 JIT Helpers
265    */
266
267    .macro dumpSwitch _regData _regScratch1 _regScratch2
268    .endm
269
270   /*
271    * Hard coded helper values.
272    */
273
274.balign 16
275
276.LdoubNeg:
277    .quad       0x8000000000000000
278
279.L64bits:
280    .quad       0xFFFFFFFFFFFFFFFF
281
282.LshiftMask2:
283    .quad       0x0000000000000000
284.LshiftMask:
285    .quad       0x000000000000003F
286
287.Lvalue64:
288    .quad       0x0000000000000040
289
290.LvaluePosInfLong:
291    .quad       0x7FFFFFFFFFFFFFFF
292
293.LvalueNegInfLong:
294    .quad       0x8000000000000000
295
296.LvalueNanLong:
297    .quad       0x0000000000000000
298
299.LintMin:
300.long   0x80000000
301
302.LintMax:
303.long   0x7FFFFFFF
304
305
306/*
307 * This is a #include, not a %include, because we want the C pre-processor
308 * to expand the macros into assembler assignment statements.
309 */
310#include "../common/asm-constants.h"
311
312#if defined(WITH_JIT)
313#include "../common/jit-config.h"
314#endif
315