1633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 2633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * cpu.h: Values of the PRId register used to match up 3633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * various MIPS cpu types. 4633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * 5633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) 6633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Copyright (C) 2004 Maciej W. Rozycki 7633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 8633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#ifndef _ASM_CPU_H 9633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define _ASM_CPU_H 10633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 11633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* Assigned Company values for bits 23:16 of the PRId Register 12633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham (CP0 register 15, select 0). As of the MIPS32 and MIPS64 specs from 13633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham MTI, the PRId register is defined in this (backwards compatible) 14633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham way: 15633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 16633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham +----------------+----------------+----------------+----------------+ 17633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham | Company Options| Company ID | Processor ID | Revision | 18633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham +----------------+----------------+----------------+----------------+ 19633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 31 24 23 16 15 8 7 20633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 21633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham I don't have docs for all the previous processors, but my impression is 22633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64 23633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham spec. 24633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham*/ 25633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 26633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_COMP_LEGACY 0x000000 27633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_COMP_MIPS 0x010000 28633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_COMP_BROADCOM 0x020000 29633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_COMP_ALCHEMY 0x030000 30633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_COMP_SIBYTE 0x040000 31633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_COMP_SANDCRAFT 0x050000 32633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_COMP_NXP 0x060000 33633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_COMP_TOSHIBA 0x070000 34633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_COMP_LSI 0x080000 35633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_COMP_LEXRA 0x0b0000 36633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 37633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 38633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 39633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Assigned values for the product ID register. In order to detect a 40633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * certain CPU type exactly eventually additional registers may need to 41633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * be examined. These are valid when 23:16 == PRID_COMP_LEGACY 42633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 43633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_R2000 0x0100 44633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_AU1_REV1 0x0100 45633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_AU1_REV2 0x0200 46633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_R3000 0x0200 /* Same as R2000A */ 47633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_R6000 0x0300 /* Same as R3000A */ 48633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_R4000 0x0400 49633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_R6000A 0x0600 50633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_R10000 0x0900 51633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_R4300 0x0b00 52633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_VR41XX 0x0c00 53633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_R12000 0x0e00 54633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_R14000 0x0f00 55633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_R8000 0x1000 56633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_PR4450 0x1200 57633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_R4600 0x2000 58633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_R4700 0x2100 59633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_TX39 0x2200 60633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_R4640 0x2200 61633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_R4650 0x2200 /* Same as R4640 */ 62633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_R5000 0x2300 63633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_TX49 0x2d00 64633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_SONIC 0x2400 65633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_MAGIC 0x2500 66633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_RM7000 0x2700 67633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */ 68633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_RM9000 0x3400 69633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_LOONGSON1 0x4200 70633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_R5432 0x5400 71633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_R5500 0x5500 72633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_LOONGSON2 0x6300 73633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 74633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_UNKNOWN 0xff00 75633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 76633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 77633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * These are the PRID's for when 23:16 == PRID_COMP_MIPS 78633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 79633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 80633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_4KC 0x8000 81633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_5KC 0x8100 82633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_20KC 0x8200 83633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_4KEC 0x8400 84633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_4KSC 0x8600 85633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_25KF 0x8800 86633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_5KE 0x8900 87633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_4KECR2 0x9000 88633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_4KEMPR2 0x9100 89633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_4KSD 0x9200 90633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_24K 0x9300 91633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_34K 0x9500 92633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_24KE 0x9600 93633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_74K 0x9700 94633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_1004K 0x9900 95633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 96633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 97633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE 98633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 99633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 100633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_SB1 0x0100 101633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_SB1A 0x1100 102633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 103633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 104633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT 105633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 106633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 107633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_SR71000 0x0400 108633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 109633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 110633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM 111633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 112633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 113633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_BCM4710 0x4000 114633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_IMP_BCM3302 0x9000 115633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 116633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 117633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Definitions for 7:0 on legacy processors 118633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 119633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 120633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_REV_MASK 0x00ff 121633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 122633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_REV_TX4927 0x0022 123633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_REV_TX4937 0x0030 124633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_REV_R4400 0x0040 125633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_REV_R3000A 0x0030 126633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_REV_R3000 0x0020 127633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_REV_R2000A 0x0010 128633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_REV_TX3912 0x0010 129633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_REV_TX3922 0x0030 130633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_REV_TX3927 0x0040 131633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_REV_VR4111 0x0050 132633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_REV_VR4181 0x0050 /* Same as VR4111 */ 133633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_REV_VR4121 0x0060 134633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_REV_VR4122 0x0070 135633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ 136633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_REV_VR4130 0x0080 137633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_REV_34K_V1_0_2 0x0022 138633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 139633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 140633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Older processors used to encode processor version and revision in two 141633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores 142633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * have switched to use the 8-bits as 3:3:2 bitfield with the last field as 143633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * the patch number. *ARGH* 144633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 145633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_REV_ENCODE_44(ver, rev) \ 146633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham ((ver) << 4 | (rev)) 147633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PRID_REV_ENCODE_332(ver, rev, patch) \ 148633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham ((ver) << 5 | (rev) << 2 | (patch)) 149633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 150633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 151633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * FPU implementation/revision register (CP1 control register 0). 152633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * 153633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * +---------------------------------+----------------+----------------+ 154633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * | 0 | Implementation | Revision | 155633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * +---------------------------------+----------------+----------------+ 156633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * 31 16 15 8 7 0 157633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 158633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 159633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define FPIR_IMP_NONE 0x0000 160633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 161633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamenum cpu_type_enum { 162633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham CPU_UNKNOWN, 163633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 164633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 165633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * R2000 class processors 166633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 167633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052, 168633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham CPU_R3081, CPU_R3081E, 169633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 170633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 171633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * R6000 class processors 172633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 173633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham CPU_R6000, CPU_R6000A, 174633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 175633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 176633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * R4000 class processors 177633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 178633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310, 179633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650, 180633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham CPU_R4700, CPU_R5000, CPU_R5000A, CPU_R5500, CPU_NEVADA, CPU_R5432, 181633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham CPU_R10000, CPU_R12000, CPU_R14000, CPU_VR41XX, CPU_VR4111, CPU_VR4121, 182633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000, 183633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham CPU_SR71000, CPU_RM9000, CPU_TX49XX, 184633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 185633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 186633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * R8000 class processors 187633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 188633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham CPU_R8000, 189633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 190633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 191633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * TX3900 class processors 192633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 193633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham CPU_TX3912, CPU_TX3922, CPU_TX3927, 194633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 195633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 196633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * MIPS32 class processors 197633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 198633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, 199633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham CPU_AU1000, CPU_AU1100, CPU_AU1200, CPU_AU1210, CPU_AU1250, CPU_AU1500, 200633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham CPU_AU1550, CPU_PR4450, CPU_BCM3302, CPU_BCM4710, 201633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 202633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 203633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * MIPS64 class processors 204633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 205633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, 206633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 207633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham CPU_LAST 208633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham}; 209633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 210633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 211633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 212633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * ISA Level encodings 213633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * 214633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 215633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_CPU_ISA_I 0x00000001 216633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_CPU_ISA_II 0x00000002 217633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_CPU_ISA_III 0x00000004 218633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_CPU_ISA_IV 0x00000008 219633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_CPU_ISA_V 0x00000010 220633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_CPU_ISA_M32R1 0x00000020 221633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_CPU_ISA_M32R2 0x00000040 222633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_CPU_ISA_M64R1 0x00000080 223633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_CPU_ISA_M64R2 0x00000100 224633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 225633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \ 226633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 ) 227633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \ 228633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2) 229633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 230633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 231633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * CPU Option encodings 232633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 233633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_CPU_TLB 0x00000001 /* CPU has TLB */ 234633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_CPU_4KEX 0x00000002 /* "R4K" exception model */ 235633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_CPU_3K_CACHE 0x00000004 /* R3000-style caches */ 236633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_CPU_4K_CACHE 0x00000008 /* R4000-style caches */ 237633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_CPU_TX39_CACHE 0x00000010 /* TX3900-style caches */ 238633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_CPU_FPU 0x00000020 /* CPU has FPU */ 239633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_CPU_32FPR 0x00000040 /* 32 dbl. prec. FP registers */ 240633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_CPU_COUNTER 0x00000080 /* Cycle count/compare */ 241633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_CPU_WATCH 0x00000100 /* watchpoint registers */ 242633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_CPU_DIVEC 0x00000200 /* dedicated interrupt vector */ 243633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_CPU_VCE 0x00000400 /* virt. coherence conflict possible */ 244633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_CPU_CACHE_CDEX_P 0x00000800 /* Create_Dirty_Exclusive CACHE op */ 245633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_CPU_CACHE_CDEX_S 0x00001000 /* ... same for seconary cache ... */ 246633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_CPU_MCHECK 0x00002000 /* Machine check exception */ 247633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_CPU_EJTAG 0x00004000 /* EJTAG exception */ 248633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_CPU_NOFPUEX 0x00008000 /* no FPU exception */ 249633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_CPU_LLSC 0x00010000 /* CPU has ll/sc instructions */ 250633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_CPU_INCLUSIVE_CACHES 0x00020000 /* P-cache subset enforced */ 251633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_CPU_PREFETCH 0x00040000 /* CPU has usable prefetch */ 252633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_CPU_VINT 0x00080000 /* CPU supports MIPSR2 vectored interrupts */ 253633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */ 254633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */ 255633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 256633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 257633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * CPU ASE encodings 258633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 259633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_ASE_MIPS16 0x00000001 /* code compression */ 260633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_ASE_MDMX 0x00000002 /* MIPS digital media extension */ 261633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */ 262633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */ 263633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */ 264633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */ 265633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 266633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 267633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif /* _ASM_CPU_H */ 268