1633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 2633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Definitions for the SGI MACE (Multimedia, Audio and Communications Engine) 3633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * 4633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * This file is subject to the terms and conditions of the GNU General Public 5633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * License. See the file "COPYING" in the main directory of this archive 6633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * for more details. 7633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * 8633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Copyright (C) 2000 Harald Koerfgen 9633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Copyright (C) 2004 Ladislav Michl 10633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 11633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 12633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#ifndef __ASM_MACE_H__ 13633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define __ASM_MACE_H__ 14633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 15633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 16633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Address map 17633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 18633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACE_BASE 0x1f000000 /* physical */ 19633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 20633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 21633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * PCI interface 22633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 23633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamstruct mace_pci { 24633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned int error_addr; 25633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned int error; 26633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_ERROR_MASTER_ABORT BIT(31) 27633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_ERROR_TARGET_ABORT BIT(30) 28633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_ERROR_DATA_PARITY_ERR BIT(29) 29633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_ERROR_RETRY_ERR BIT(28) 30633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_ERROR_ILLEGAL_CMD BIT(27) 31633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_ERROR_SYSTEM_ERR BIT(26) 32633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_ERROR_INTERRUPT_TEST BIT(25) 33633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_ERROR_PARITY_ERR BIT(24) 34633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_ERROR_OVERRUN BIT(23) 35633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_ERROR_RSVD BIT(22) 36633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_ERROR_MEMORY_ADDR BIT(21) 37633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_ERROR_CONFIG_ADDR BIT(20) 38633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_ERROR_MASTER_ABORT_ADDR_VALID BIT(19) 39633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_ERROR_TARGET_ABORT_ADDR_VALID BIT(18) 40633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_ERROR_DATA_PARITY_ADDR_VALID BIT(17) 41633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_ERROR_RETRY_ADDR_VALID BIT(16) 42633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_ERROR_SIG_TABORT BIT(4) 43633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_ERROR_DEVSEL_MASK 0xc0 44633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_ERROR_DEVSEL_FAST 0 45633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_ERROR_DEVSEL_MED 0x40 46633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_ERROR_DEVSEL_SLOW 0x80 47633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_ERROR_FBB BIT(1) 48633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_ERROR_66MHZ BIT(0) 49633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned int control; 50633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_CONTROL_INT(x) BIT(x) 51633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_CONTROL_INT_MASK 0xff 52633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_CONTROL_SERR_ENA BIT(8) 53633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_CONTROL_ARB_N6 BIT(9) 54633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_CONTROL_PARITY_ERR BIT(10) 55633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_CONTROL_MRMRA_ENA BIT(11) 56633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_CONTROL_ARB_N3 BIT(12) 57633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_CONTROL_ARB_N4 BIT(13) 58633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_CONTROL_ARB_N5 BIT(14) 59633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_CONTROL_PARK_LIU BIT(15) 60633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_CONTROL_INV_INT(x) BIT(16+x) 61633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_CONTROL_INV_INT_MASK 0x00ff0000 62633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_CONTROL_OVERRUN_INT BIT(24) 63633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_CONTROL_PARITY_INT BIT(25) 64633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_CONTROL_SERR_INT BIT(26) 65633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_CONTROL_IT_INT BIT(27) 66633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_CONTROL_RE_INT BIT(28) 67633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_CONTROL_DPED_INT BIT(29) 68633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_CONTROL_TAR_INT BIT(30) 69633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_CONTROL_MAR_INT BIT(31) 70633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned int rev; 71633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham unsigned int _pad[0xcf8/4 - 4]; 72633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned int config_addr; 73633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham union { 74633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned char b[4]; 75633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned short w[2]; 76633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned int l; 77633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham } config_data; 78633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham}; 79633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_LOW_MEMORY 0x1a000000 80633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_LOW_IO 0x18000000 81633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_SWAPPED_VIEW 0 82633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_NATIVE_VIEW 0x40000000 83633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_IO 0x80000000 84633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_HI_MEMORY 0x280000000 85633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPCI_HI_IO 0x100000000 86633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 87633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 88633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Video interface 89633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 90633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamstruct mace_video { 91633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham unsigned long xxx; /* later... */ 92633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham}; 93633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 94633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 95633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Ethernet interface 96633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 97633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamstruct mace_ethernet { 98633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long mac_ctrl; 99633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long int_stat; 100633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long dma_ctrl; 101633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long timer; 102633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long tx_int_al; 103633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long rx_int_al; 104633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long tx_info; 105633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long tx_info_al; 106633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long rx_buff; 107633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long rx_buff_al1; 108633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long rx_buff_al2; 109633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long diag; 110633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long phy_data; 111633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long phy_regs; 112633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long phy_trans_go; 113633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long backoff_seed; 114633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /*===================================*/ 115633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long imq_reserved[4]; 116633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long mac_addr; 117633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long mac_addr2; 118633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long mcast_filter; 119633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long tx_ring_base; 120633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* Following are read-only registers for debugging */ 121633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long tx_pkt1_hdr; 122633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long tx_pkt1_ptr[3]; 123633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long tx_pkt2_hdr; 124633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long tx_pkt2_ptr[3]; 125633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /*===================================*/ 126633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long rx_fifo; 127633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham}; 128633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 129633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 130633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Peripherals 131633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 132633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 133633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* Audio registers */ 134633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamstruct mace_audio { 135633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long control; 136633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long codec_control; /* codec status control */ 137633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long codec_mask; /* codec status input mask */ 138633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long codec_read; /* codec status read data */ 139633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham struct { 140633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long control; /* channel control */ 141633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long read_ptr; /* channel read pointer */ 142633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long write_ptr; /* channel write pointer */ 143633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long depth; /* channel depth */ 144633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham } chan[3]; 145633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham}; 146633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 147633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 148633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* register definitions for parallel port DMA */ 149633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamstruct mace_parport { 150633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 0 - do nothing, 151633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * 1 - pulse terminal count to the device after buffer is drained */ 152633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPAR_CONTEXT_LASTFLAG BIT(63) 153633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* Should not cross 4K page boundary */ 154633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPAR_CONTEXT_DATA_BOUND 0x0000000000001000UL 155633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPAR_CONTEXT_DATALEN_MASK 0x00000fff00000000UL 156633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPAR_CONTEXT_DATALEN_SHIFT 32 157633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* Can be arbitrarily aligned on any byte boundary on output, 158633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * 64 byte aligned on input */ 159633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPAR_CONTEXT_BASEADDR_MASK 0x00000000ffffffffUL 160633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u64 context_a; 161633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u64 context_b; 162633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 0 - mem->device, 1 - device->mem */ 163633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPAR_CTLSTAT_DIRECTION BIT(0) 164633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 0 - channel frozen, 1 - channel enabled */ 165633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPAR_CTLSTAT_ENABLE BIT(1) 166633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 0 - channel active, 1 - complete channel reset */ 167633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPAR_CTLSTAT_RESET BIT(2) 168633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPAR_CTLSTAT_CTXB_VALID BIT(3) 169633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPAR_CTLSTAT_CTXA_VALID BIT(4) 170633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u64 cntlstat; /* Control/Status register */ 171633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPAR_DIAG_CTXINUSE BIT(0) 172633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* 1 - Dma engine is enabled and processing something */ 173633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPAR_DIAG_DMACTIVE BIT(1) 174633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* Counter of bytes left */ 175633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPAR_DIAG_CTRMASK 0x0000000000003ffcUL 176633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEPAR_DIAG_CTRSHIFT 2 177633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u64 diagnostic; /* RO: diagnostic register */ 178633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham}; 179633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 180633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* ISA Control and DMA registers */ 181633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamstruct mace_isactrl { 182633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long ringbase; 183633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEISA_RINGBUFFERS_SIZE (8 * 4096) 184633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 185633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long misc; 186633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEISA_FLASH_WE BIT(0) /* 1=> Enable FLASH writes */ 187633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEISA_PWD_CLEAR BIT(1) /* 1=> PWD CLEAR jumper detected */ 188633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEISA_NIC_DEASSERT BIT(2) 189633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEISA_NIC_DATA BIT(3) 190633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEISA_LED_RED BIT(4) /* 0=> Illuminate red LED */ 191633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEISA_LED_GREEN BIT(5) /* 0=> Illuminate green LED */ 192633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEISA_DP_RAM_ENABLE BIT(6) 193633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 194633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long istat; 195633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long imask; 196633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEISA_AUDIO_SW_INT BIT(0) 197633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEISA_AUDIO_SC_INT BIT(1) 198633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEISA_AUDIO1_DMAT_INT BIT(2) 199633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEISA_AUDIO1_OF_INT BIT(3) 200633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEISA_AUDIO2_DMAT_INT BIT(4) 201633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEISA_AUDIO2_MERR_INT BIT(5) 202633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEISA_AUDIO3_DMAT_INT BIT(6) 203633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEISA_AUDIO3_MERR_INT BIT(7) 204633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEISA_RTC_INT BIT(8) 205633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEISA_KEYB_INT BIT(9) 206633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEISA_KEYB_POLL_INT BIT(10) 207633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEISA_MOUSE_INT BIT(11) 208633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEISA_MOUSE_POLL_INT BIT(12) 209633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEISA_TIMER0_INT BIT(13) 210633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEISA_TIMER1_INT BIT(14) 211633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEISA_TIMER2_INT BIT(15) 212633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEISA_PARALLEL_INT BIT(16) 213633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEISA_PAR_CTXA_INT BIT(17) 214633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEISA_PAR_CTXB_INT BIT(18) 215633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEISA_PAR_MERR_INT BIT(19) 216633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEISA_SERIAL1_INT BIT(20) 217633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEISA_SERIAL1_TDMAT_INT BIT(21) 218633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEISA_SERIAL1_TDMAPR_INT BIT(22) 219633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEISA_SERIAL1_TDMAME_INT BIT(23) 220633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEISA_SERIAL1_RDMAT_INT BIT(24) 221633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEISA_SERIAL1_RDMAOR_INT BIT(25) 222633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEISA_SERIAL2_INT BIT(26) 223633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEISA_SERIAL2_TDMAT_INT BIT(27) 224633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEISA_SERIAL2_TDMAPR_INT BIT(28) 225633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEISA_SERIAL2_TDMAME_INT BIT(29) 226633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEISA_SERIAL2_RDMAT_INT BIT(30) 227633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEISA_SERIAL2_RDMAOR_INT BIT(31) 228633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 229633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long _pad[0x2000/8 - 4]; 230633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 231633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long dp_ram[0x400]; 232633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham struct mace_parport parport; 233633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham}; 234633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 235633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* Keyboard & Mouse registers 236633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * -> drivers/input/serio/maceps2.c */ 237633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamstruct mace_ps2port { 238633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long tx; 239633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long rx; 240633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long control; 241633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long status; 242633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham}; 243633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 244633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamstruct mace_ps2 { 245633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham struct mace_ps2port keyb; 246633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham struct mace_ps2port mouse; 247633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham}; 248633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 249633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* I2C registers 250633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * -> drivers/i2c/algos/i2c-algo-sgi.c */ 251633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamstruct mace_i2c { 252633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long config; 253633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEI2C_RESET BIT(0) 254633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEI2C_FAST BIT(1) 255633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEI2C_DATA_OVERRIDE BIT(2) 256633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEI2C_CLOCK_OVERRIDE BIT(3) 257633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEI2C_DATA_STATUS BIT(4) 258633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACEI2C_CLOCK_STATUS BIT(5) 259633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long control; 260633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long data; 261633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham}; 262633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 263633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* Timer registers */ 264633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamtypedef union { 265633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long ust_msc; 266633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham struct reg { 267633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned int ust; 268633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned int msc; 269633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham } reg; 270633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham} timer_reg; 271633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 272633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamstruct mace_timers { 273633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long ust; 274633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MACE_UST_PERIOD_NS 960 275633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 276633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long compare1; 277633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long compare2; 278633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long compare3; 279633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 280633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham timer_reg audio_in; 281633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham timer_reg audio_out1; 282633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham timer_reg audio_out2; 283633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham timer_reg video_in1; 284633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham timer_reg video_in2; 285633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham timer_reg video_out; 286633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham}; 287633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 288633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamstruct mace_perif { 289633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham struct mace_audio audio; 290633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham char _pad0[0x10000 - sizeof(struct mace_audio)]; 291633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 292633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham struct mace_isactrl ctrl; 293633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham char _pad1[0x10000 - sizeof(struct mace_isactrl)]; 294633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 295633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham struct mace_ps2 ps2; 296633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham char _pad2[0x10000 - sizeof(struct mace_ps2)]; 297633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 298633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham struct mace_i2c i2c; 299633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham char _pad3[0x10000 - sizeof(struct mace_i2c)]; 300633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 301633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham struct mace_timers timers; 302633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham char _pad4[0x10000 - sizeof(struct mace_timers)]; 303633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham}; 304633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 305633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 306633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 307633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * ISA peripherals 308633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 309633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 310633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* Parallel port */ 311633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamstruct mace_parallel { 312633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham}; 313633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 314633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamstruct mace_ecp1284 { /* later... */ 315633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham}; 316633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 317633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* Serial port */ 318633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamstruct mace_serial { 319633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned long xxx; /* later... */ 320633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham}; 321633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 322633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamstruct mace_isa { 323633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham struct mace_parallel parallel; 324633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham char _pad1[0x8000 - sizeof(struct mace_parallel)]; 325633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 326633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham struct mace_ecp1284 ecp1284; 327633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham char _pad2[0x8000 - sizeof(struct mace_ecp1284)]; 328633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 329633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham struct mace_serial serial1; 330633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham char _pad3[0x8000 - sizeof(struct mace_serial)]; 331633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 332633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham struct mace_serial serial2; 333633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham char _pad4[0x8000 - sizeof(struct mace_serial)]; 334633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 335633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile unsigned char rtc[0x10000]; 336633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham}; 337633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 338633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamstruct sgi_mace { 339633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham char _reserved[0x80000]; 340633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 341633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham struct mace_pci pci; 342633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham char _pad0[0x80000 - sizeof(struct mace_pci)]; 343633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 344633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham struct mace_video video_in1; 345633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham char _pad1[0x80000 - sizeof(struct mace_video)]; 346633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 347633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham struct mace_video video_in2; 348633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham char _pad2[0x80000 - sizeof(struct mace_video)]; 349633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 350633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham struct mace_video video_out; 351633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham char _pad3[0x80000 - sizeof(struct mace_video)]; 352633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 353633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham struct mace_ethernet eth; 354633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham char _pad4[0x80000 - sizeof(struct mace_ethernet)]; 355633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 356633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham struct mace_perif perif; 357633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham char _pad5[0x80000 - sizeof(struct mace_perif)]; 358633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 359633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham struct mace_isa isa; 360633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham char _pad6[0x80000 - sizeof(struct mace_isa)]; 361633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham}; 362633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 363633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamextern struct sgi_mace __iomem *mace; 364633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 365633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif /* __ASM_MACE_H__ */ 366