1//===- TargetRegisterInfo.cpp - Target Register Information Implementation ===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the TargetRegisterInfo interface.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetMachine.h"
15#include "llvm/Target/TargetRegisterInfo.h"
16#include "llvm/ADT/BitVector.h"
17#include "llvm/Support/raw_ostream.h"
18
19using namespace llvm;
20
21TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
22                             regclass_iterator RCB, regclass_iterator RCE,
23                             const char *const *subregindexnames)
24  : InfoDesc(ID), SubRegIndexNames(subregindexnames),
25    RegClassBegin(RCB), RegClassEnd(RCE) {
26}
27
28TargetRegisterInfo::~TargetRegisterInfo() {}
29
30void PrintReg::print(raw_ostream &OS) const {
31  if (!Reg)
32    OS << "%noreg";
33  else if (TargetRegisterInfo::isStackSlot(Reg))
34    OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg);
35  else if (TargetRegisterInfo::isVirtualRegister(Reg))
36    OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg);
37  else if (TRI && Reg < TRI->getNumRegs())
38    OS << '%' << TRI->getName(Reg);
39  else
40    OS << "%physreg" << Reg;
41  if (SubIdx) {
42    if (TRI)
43      OS << ':' << TRI->getSubRegIndexName(SubIdx);
44    else
45      OS << ":sub(" << SubIdx << ')';
46  }
47}
48
49void PrintRegUnit::print(raw_ostream &OS) const {
50  // Generic printout when TRI is missing.
51  if (!TRI) {
52    OS << "Unit~" << Unit;
53    return;
54  }
55
56  // Check for invalid register units.
57  if (Unit >= TRI->getNumRegUnits()) {
58    OS << "BadUnit~" << Unit;
59    return;
60  }
61
62  // Normal units have at least one root.
63  MCRegUnitRootIterator Roots(Unit, TRI);
64  assert(Roots.isValid() && "Unit has no roots.");
65  OS << TRI->getName(*Roots);
66  for (++Roots; Roots.isValid(); ++Roots)
67    OS << '~' << TRI->getName(*Roots);
68}
69
70/// getAllocatableClass - Return the maximal subclass of the given register
71/// class that is alloctable, or NULL.
72const TargetRegisterClass *
73TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const {
74  if (!RC || RC->isAllocatable())
75    return RC;
76
77  const unsigned *SubClass = RC->getSubClassMask();
78  for (unsigned Base = 0, BaseE = getNumRegClasses();
79       Base < BaseE; Base += 32) {
80    unsigned Idx = Base;
81    for (unsigned Mask = *SubClass++; Mask; Mask >>= 1) {
82      unsigned Offset = CountTrailingZeros_32(Mask);
83      const TargetRegisterClass *SubRC = getRegClass(Idx + Offset);
84      if (SubRC->isAllocatable())
85        return SubRC;
86      Mask >>= Offset;
87      Idx += Offset + 1;
88    }
89  }
90  return NULL;
91}
92
93/// getMinimalPhysRegClass - Returns the Register Class of a physical
94/// register of the given type, picking the most sub register class of
95/// the right type that contains this physreg.
96const TargetRegisterClass *
97TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, EVT VT) const {
98  assert(isPhysicalRegister(reg) && "reg must be a physical register");
99
100  // Pick the most sub register class of the right type that contains
101  // this physreg.
102  const TargetRegisterClass* BestRC = 0;
103  for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){
104    const TargetRegisterClass* RC = *I;
105    if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
106        (!BestRC || BestRC->hasSubClass(RC)))
107      BestRC = RC;
108  }
109
110  assert(BestRC && "Couldn't find the register class");
111  return BestRC;
112}
113
114/// getAllocatableSetForRC - Toggle the bits that represent allocatable
115/// registers for the specific register class.
116static void getAllocatableSetForRC(const MachineFunction &MF,
117                                   const TargetRegisterClass *RC, BitVector &R){
118  assert(RC->isAllocatable() && "invalid for nonallocatable sets");
119  ArrayRef<uint16_t> Order = RC->getRawAllocationOrder(MF);
120  for (unsigned i = 0; i != Order.size(); ++i)
121    R.set(Order[i]);
122}
123
124BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF,
125                                          const TargetRegisterClass *RC) const {
126  BitVector Allocatable(getNumRegs());
127  if (RC) {
128    // A register class with no allocatable subclass returns an empty set.
129    const TargetRegisterClass *SubClass = getAllocatableClass(RC);
130    if (SubClass)
131      getAllocatableSetForRC(MF, SubClass, Allocatable);
132  } else {
133    for (TargetRegisterInfo::regclass_iterator I = regclass_begin(),
134         E = regclass_end(); I != E; ++I)
135      if ((*I)->isAllocatable())
136        getAllocatableSetForRC(MF, *I, Allocatable);
137  }
138
139  // Mask out the reserved registers
140  BitVector Reserved = getReservedRegs(MF);
141  Allocatable &= Reserved.flip();
142
143  return Allocatable;
144}
145
146static inline
147const TargetRegisterClass *firstCommonClass(const uint32_t *A,
148                                            const uint32_t *B,
149                                            const TargetRegisterInfo *TRI) {
150  for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; I += 32)
151    if (unsigned Common = *A++ & *B++)
152      return TRI->getRegClass(I + CountTrailingZeros_32(Common));
153  return 0;
154}
155
156const TargetRegisterClass *
157TargetRegisterInfo::getCommonSubClass(const TargetRegisterClass *A,
158                                      const TargetRegisterClass *B) const {
159  // First take care of the trivial cases.
160  if (A == B)
161    return A;
162  if (!A || !B)
163    return 0;
164
165  // Register classes are ordered topologically, so the largest common
166  // sub-class it the common sub-class with the smallest ID.
167  return firstCommonClass(A->getSubClassMask(), B->getSubClassMask(), this);
168}
169
170const TargetRegisterClass *
171TargetRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
172                                             const TargetRegisterClass *B,
173                                             unsigned Idx) const {
174  assert(A && B && "Missing register class");
175  assert(Idx && "Bad sub-register index");
176
177  // Find Idx in the list of super-register indices.
178  for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI)
179    if (RCI.getSubReg() == Idx)
180      // The bit mask contains all register classes that are projected into B
181      // by Idx. Find a class that is also a sub-class of A.
182      return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this);
183  return 0;
184}
185
186const TargetRegisterClass *TargetRegisterInfo::
187getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
188                       const TargetRegisterClass *RCB, unsigned SubB,
189                       unsigned &PreA, unsigned &PreB) const {
190  assert(RCA && SubA && RCB && SubB && "Invalid arguments");
191
192  // Search all pairs of sub-register indices that project into RCA and RCB
193  // respectively. This is quadratic, but usually the sets are very small. On
194  // most targets like X86, there will only be a single sub-register index
195  // (e.g., sub_16bit projecting into GR16).
196  //
197  // The worst case is a register class like DPR on ARM.
198  // We have indices dsub_0..dsub_7 projecting into that class.
199  //
200  // It is very common that one register class is a sub-register of the other.
201  // Arrange for RCA to be the larger register so the answer will be found in
202  // the first iteration. This makes the search linear for the most common
203  // case.
204  const TargetRegisterClass *BestRC = 0;
205  unsigned *BestPreA = &PreA;
206  unsigned *BestPreB = &PreB;
207  if (RCA->getSize() < RCB->getSize()) {
208    std::swap(RCA, RCB);
209    std::swap(SubA, SubB);
210    std::swap(BestPreA, BestPreB);
211  }
212
213  // Also terminate the search one we have found a register class as small as
214  // RCA.
215  unsigned MinSize = RCA->getSize();
216
217  for (SuperRegClassIterator IA(RCA, this, true); IA.isValid(); ++IA) {
218    unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA);
219    for (SuperRegClassIterator IB(RCB, this, true); IB.isValid(); ++IB) {
220      // Check if a common super-register class exists for this index pair.
221      const TargetRegisterClass *RC =
222        firstCommonClass(IA.getMask(), IB.getMask(), this);
223      if (!RC || RC->getSize() < MinSize)
224        continue;
225
226      // The indexes must compose identically: PreA+SubA == PreB+SubB.
227      unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB);
228      if (FinalA != FinalB)
229        continue;
230
231      // Is RC a better candidate than BestRC?
232      if (BestRC && RC->getSize() >= BestRC->getSize())
233        continue;
234
235      // Yes, RC is the smallest super-register seen so far.
236      BestRC = RC;
237      *BestPreA = IA.getSubReg();
238      *BestPreB = IB.getSubReg();
239
240      // Bail early if we reached MinSize. We won't find a better candidate.
241      if (BestRC->getSize() == MinSize)
242        return BestRC;
243    }
244  }
245  return BestRC;
246}
247