1###########################################################
2## Commands for running tblgen to compile a td file
3##########################################################
4define transform-td-to-out
5$(if $(LOCAL_IS_HOST_MODULE),	\
6	$(call transform-host-td-to-out,$(1)),	\
7	$(call transform-device-td-to-out,$(1)))
8endef
9
10###########################################################
11## TableGen: Compile .td files to .inc.
12###########################################################
13ifeq ($(LOCAL_MODULE_CLASS),)
14	LOCAL_MODULE_CLASS := STATIC_LIBRARIES
15endif
16
17ifneq ($(strip $(TBLGEN_TABLES)),)
18
19intermediates := $(call local-intermediates-dir)
20tblgen_gen_tables := $(addprefix $(intermediates)/,$(TBLGEN_TABLES))
21LOCAL_GENERATED_SOURCES += $(tblgen_gen_tables)
22
23tblgen_source_dir := $(LOCAL_PATH)
24ifneq ($(TBLGEN_TD_DIR),)
25tblgen_source_dir := $(TBLGEN_TD_DIR)
26endif
27
28ifneq ($(filter %GenRegisterNames.inc,$(tblgen_gen_tables)),)
29$(intermediates)/%GenRegisterNames.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
30$(intermediates)/%GenRegisterNames.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
31	$(call transform-td-to-out,register-enums)
32endif
33
34ifneq ($(filter %GenRegisterInfo.h.inc,$(tblgen_gen_tables)),)
35$(intermediates)/%GenRegisterInfo.h.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
36$(intermediates)/%GenRegisterInfo.h.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
37	$(call transform-td-to-out,register-desc-header)
38endif
39
40ifneq ($(filter %GenRegisterInfo.inc,$(tblgen_gen_tables)),)
41$(intermediates)/%GenRegisterInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
42$(intermediates)/%GenRegisterInfo.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
43	$(call transform-td-to-out,register-desc)
44endif
45
46ifneq ($(filter %GenInstrNames.inc,$(tblgen_gen_tables)),)
47$(intermediates)/%GenInstrNames.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
48$(intermediates)/%GenInstrNames.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
49	$(call transform-td-to-out,instr-enums)
50endif
51
52ifneq ($(filter %GenInstrInfo.inc,$(tblgen_gen_tables)),)
53$(intermediates)/%GenInstrInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
54$(intermediates)/%GenInstrInfo.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
55	$(call transform-td-to-out,instr-desc)
56endif
57
58ifneq ($(filter %GenAsmWriter.inc,$(tblgen_gen_tables)),)
59$(intermediates)/%GenAsmWriter.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
60$(intermediates)/%GenAsmWriter.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
61	$(call transform-td-to-out,asm-writer)
62endif
63
64ifneq ($(filter %GenAsmWriter1.inc,$(tblgen_gen_tables)),)
65$(intermediates)/%GenAsmWriter1.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
66$(intermediates)/%GenAsmWriter1.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
67	$(call transform-td-to-out,asm-writer -asmwriternum=1)
68endif
69
70ifneq ($(filter %GenAsmMatcher.inc,$(tblgen_gen_tables)),)
71$(intermediates)/%GenAsmMatcher.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
72$(intermediates)/%GenAsmMatcher.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
73	$(call transform-td-to-out,asm-matcher)
74endif
75
76ifneq ($(filter %GenCodeEmitter.inc,$(tblgen_gen_tables)),)
77$(intermediates)/%GenCodeEmitter.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
78$(intermediates)/%GenCodeEmitter.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
79	$(call transform-td-to-out,emitter)
80endif
81
82ifneq ($(filter %GenMCCodeEmitter.inc,$(tblgen_gen_tables)),)
83$(intermediates)/%GenMCCodeEmitter.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
84$(intermediates)/%GenMCCodeEmitter.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
85	$(call transform-td-to-out,emitter -mc-emitter)
86endif
87
88ifneq ($(filter %GenMCPseudoLowering.inc,$(tblgen_gen_tables)),)
89$(intermediates)/%GenMCPseudoLowering.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
90$(intermediates)/%GenMCPseudoLowering.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
91	$(call transform-td-to-out,pseudo-lowering)
92endif
93
94ifneq ($(filter %GenDAGISel.inc,$(tblgen_gen_tables)),)
95$(intermediates)/%GenDAGISel.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
96$(intermediates)/%GenDAGISel.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
97	$(call transform-td-to-out,dag-isel)
98endif
99
100ifneq ($(filter %GenDisassemblerTables.inc,$(tblgen_gen_tables)),)
101$(intermediates)/%GenDisassemblerTables.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
102$(intermediates)/%GenDisassemblerTables.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
103	$(call transform-td-to-out,disassembler)
104endif
105
106ifneq ($(filter %GenEDInfo.inc,$(tblgen_gen_tables)),)
107$(intermediates)/%GenEDInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
108$(intermediates)/%GenEDInfo.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
109	$(call transform-td-to-out,enhanced-disassembly-info)
110endif
111
112ifneq ($(filter %GenFastISel.inc,$(tblgen_gen_tables)),)
113$(intermediates)/%GenFastISel.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
114$(intermediates)/%GenFastISel.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
115	$(call transform-td-to-out,fast-isel)
116endif
117
118ifneq ($(filter %GenSubtargetInfo.inc,$(tblgen_gen_tables)),)
119$(intermediates)/%GenSubtargetInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
120$(intermediates)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
121	$(call transform-td-to-out,subtarget)
122endif
123
124ifneq ($(filter %GenCallingConv.inc,$(tblgen_gen_tables)),)
125$(intermediates)/%GenCallingConv.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
126$(intermediates)/%GenCallingConv.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
127	$(call transform-td-to-out,callingconv)
128endif
129
130ifneq ($(filter %GenIntrinsics.inc,$(tblgen_gen_tables)),)
131$(intermediates)/%GenIntrinsics.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
132$(intermediates)/%GenIntrinsics.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
133	$(call transform-td-to-out,tgt_intrinsics)
134endif
135
136ifneq ($(findstring ARMGenDecoderTables.inc,$(tblgen_gen_tables)),)
137$(intermediates)/ARMGenDecoderTables.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE)
138$(intermediates)/ARMGenDecoderTables.inc: $(tblgen_source_dir)/ARM.td $(TBLGEN)
139	$(call transform-td-to-out,arm-decoder)
140endif
141
142endif
143