17a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown# 27a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown# Intel Atom (Silverthorne) unit masks 37a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown# 47a33c86eb98056ef0570c99e713214f8dc56b6efJeff Browninclude:i386/arch_perfmon 57a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:store_forwards type:mandatory default:0x81 67a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x81 good Good store forwards 77a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:segment_reg_loads type:mandatory default:0x00 87a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x00 any Number of segment register loads 97a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:simd_prefetch type:bitmask default:0x01 107a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x01 prefetcht0 Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed 117a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x06 sw_l2 Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed 127a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x08 prefetchnta Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed 137a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:data_tlb_misses type:bitmask default:0x07 147a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x07 dtlb_miss Memory accesses that missed the DTLB 157a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x05 dtlb_miss_ld DTLB misses due to load operations 167a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x09 l0_dtlb_miss_ld L0_DTLB misses due to load operations 177a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x06 dtlb_miss_st DTLB misses due to store operations 187a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:page_walks type:bitmask default:0x03 197a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x03 walks Number of page-walks executed 207a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x03 cycles Duration of page-walks in core cycles 217a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:x87_comp_ops_exe type:bitmask default:0x81 227a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x01 s Floating point computational micro-ops executed 237a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x81 ar Floating point computational micro-ops retired 247a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:fp_assist type:mandatory default:0x81 257a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x81 ar Floating point assists 267a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:mul type:bitmask default:0x01 277a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x01 s Multiply operations executed 287a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x81 ar Multiply operations retired 297a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:div type:bitmask default:0x01 307a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x01 s Divide operations executed 317a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x81 ar Divide operations retired 327a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:l2_rqsts type:bitmask default:0x41 337a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x41 i_state L2 cache demand requests from this core that missed the L2 347a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x4F mesi L2 cache demand requests from this core 357a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:cpu_clk_unhalted type:bitmask default:0x00 367a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x00 core_p Core cycles when core is not halted 377a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x01 bus Bus cycles when core is not halted 387a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x02 no_other Bus cycles when core is active and the other is halted 397a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:l1d_cache type:bitmask default:0x21 407a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x21 ld L1 Cacheable Data Reads 417a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x22 st L1 Cacheable Data Writes 427a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:icache type:bitmask default:0x03 437a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x03 accesses Instruction fetches 447a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x02 misses Icache miss 457a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:itlb type:bitmask default:0x04 467a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x04 flush ITLB flushes 477a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x02 misses ITLB misses 487a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:macro_insts type:exclusive default:0x03 497a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x02 cisc_decoded CISC macro instructions decoded 507a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x03 all_decoded All Instructions decoded 517a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:simd_uops_exec type:exclusive default:0x80 527a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x00 s SIMD micro-ops executed (excluding stores) 537a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x80 ar SIMD micro-ops retired (excluding stores) 547a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:simd_sat_uop_exec type:bitmask default:0x00 557a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x00 s SIMD saturated arithmetic micro-ops executed 567a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x80 ar SIMD saturated arithmetic micro-ops retired 577a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:simd_uop_type_exec type:bitmask default:0x01 587a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x01 s SIMD packed multiply microops executed 597a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x81 ar SIMD packed multiply microops retired 607a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x02 s SIMD packed shift micro-ops executed 617a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x82 ar SIMD packed shift micro-ops retired 627a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x04 s SIMD pack micro-ops executed 637a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x84 ar SIMD pack micro-ops retired 647a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x08 s SIMD unpack micro-ops executed 657a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x88 ar SIMD unpack micro-ops retired 667a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x10 s SIMD packed logical microops executed 677a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x90 ar SIMD packed logical microops retired 687a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x20 s SIMD packed arithmetic micro-ops executed 697a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0xA0 ar SIMD packed arithmetic micro-ops retired 707a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:uops_retired type:mandatory default:0x10 717a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x10 any Micro-ops retired 727a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:br_inst_retired type:bitmask default:0x00 737a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x00 any Retired branch instructions 747a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x01 pred_not_taken Retired branch instructions that were predicted not-taken 757a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x02 mispred_not_taken Retired branch instructions that were mispredicted not-taken 767a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x04 pred_taken Retired branch instructions that were predicted taken 777a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x08 mispred_taken Retired branch instructions that were mispredicted taken 787a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x0A mispred Retired mispredicted branch instructions (precise event) 797a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x0C taken Retired taken branch instructions 807a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x0F any1 Retired branch instructions 817a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:cycles_int_masked type:bitmask default:0x01 827a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x01 cycles_int_masked Cycles during which interrupts are disabled 837a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x02 cycles_int_pending_and_masked Cycles during which interrupts are pending and disabled 847a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:simd_inst_retired type:bitmask default:0x01 857a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x01 packed_single Retired Streaming SIMD Extensions (SSE) packed-single instructions 867a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x02 scalar_single Retired Streaming SIMD Extensions (SSE) scalar-single instructions 877a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x04 packed_double Retired Streaming SIMD Extensions 2 (SSE2) packed-double instructions 887a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x08 scalar_double Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions 897a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x10 vector Retired Streaming SIMD Extensions 2 (SSE2) vector instructions 907a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x1F any Retired Streaming SIMD instructions 917a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:simd_comp_inst_retired type:bitmask default:0x01 927a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x01 packed_single Retired computational Streaming SIMD Extensions (SSE) packed-single instructions 937a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x02 scalar_single Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions 947a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x04 packed_double Retired computational Streaming SIMD Extensions 2 (SSE2) packed-double instructions 957a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x08 scalar_double Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions 967a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:mem_load_retired type:bitmask default:0x01 977a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x01 l2_hit Retired loads that hit the L2 cache (precise event) 987a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x02 l2_miss Retired loads that miss the L2 cache (precise event) 997a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x04 dtlb_miss Retired loads that miss the DTLB (precise event) 1007a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:thermal_trip type:mandatory default:0xc0 1017a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0xc0 thermal_trip Number of thermal trips. 1027a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown# 18-11 1037a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:core type:bitmask default:0x180 1047a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x180 all All cores. 1057a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x080 this This Core. 1067a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown# 18-12 1077a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:agent type:bitmask default:0x00 1087a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x00 this This agent 1097a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x40 any Include any agents 1107a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown# 18-13 1117a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:prefetch type:bitmask default:0x60 1127a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x60 all All inclusive 1137a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x20 hw Hardware prefetch only 1147a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x00 exclude_hw Exclude hardware prefetch 1157a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown# 18-14 1167a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brownname:mesi type:bitmask default:0x0f 1177a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x08 modified Counts modified state 1187a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x04 exclusive Counts exclusive state 1197a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x02 shared Counts shared state 1207a33c86eb98056ef0570c99e713214f8dc56b6efJeff Brown 0x01 invalid Counts invalid state 121