exec-all.h revision 5389aa19033153c09556d1362a8b8a56abccb8f5 
1/*
2 * internal execution defines for qemu
3 *
4 *  Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
19 */
20
21#ifndef _EXEC_ALL_H_
22#define _EXEC_ALL_H_
23
24#include "qemu-common.h"
25
26/* allow to see translation results - the slowdown should be negligible, so we leave it */
27#define DEBUG_DISAS
28
29/* is_jmp field values */
30#define DISAS_NEXT    0 /* next instruction can be analyzed */
31#define DISAS_JUMP    1 /* only pc was modified dynamically */
32#define DISAS_UPDATE  2 /* cpu state was modified dynamically */
33#define DISAS_TB_JUMP 3 /* only pc was modified statically */
34
35typedef struct TranslationBlock TranslationBlock;
36
37/* XXX: make safe guess about sizes */
38#define MAX_OP_PER_INSTR 64
39/* A Call op needs up to 6 + 2N parameters (N = number of arguments).  */
40#define MAX_OPC_PARAM 10
41#define OPC_BUF_SIZE 2048
42#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
43
44/* Maximum size a TCG op can expand to.  This is complicated because a
45   single op may require several host instructions and regirster reloads.
46   For now take a wild guess at 128 bytes, which should allow at least
47   a couple of fixup instructions per argument.  */
48#define TCG_MAX_OP_SIZE 128
49
50#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
51
52extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
53extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
54extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
55extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
56extern uint16_t gen_opc_icount[OPC_BUF_SIZE];
57extern target_ulong gen_opc_jump_pc[2];
58extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];
59
60#include "qemu-log.h"
61
62void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
63void gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
64void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
65                 unsigned long searched_pc, int pc_pos, void *puc);
66
67unsigned long code_gen_max_block_size(void);
68void cpu_gen_init(void);
69int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
70                 int *gen_code_size_ptr);
71int cpu_restore_state(struct TranslationBlock *tb,
72                      CPUState *env, unsigned long searched_pc,
73                      void *puc);
74int cpu_restore_state_copy(struct TranslationBlock *tb,
75                           CPUState *env, unsigned long searched_pc,
76                           void *puc);
77void cpu_resume_from_signal(CPUState *env1, void *puc);
78void cpu_io_recompile(CPUState *env, void *retaddr);
79TranslationBlock *tb_gen_code(CPUState *env,
80                              target_ulong pc, target_ulong cs_base, int flags,
81                              int cflags);
82void cpu_exec_init(CPUState *env);
83void QEMU_NORETURN cpu_loop_exit(void);
84int page_unprotect(target_ulong address, unsigned long pc, void *puc);
85void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
86                                   int is_cpu_write_access);
87void tb_invalidate_page_range(target_ulong start, target_ulong end);
88void tlb_flush_page(CPUState *env, target_ulong addr);
89void tlb_flush(CPUState *env, int flush_global);
90int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
91                      target_phys_addr_t paddr, int prot,
92                      int mmu_idx, int is_softmmu);
93static inline int tlb_set_page(CPUState *env1, target_ulong vaddr,
94                               target_phys_addr_t paddr, int prot,
95                               int mmu_idx, int is_softmmu)
96{
97    if (prot & PAGE_READ)
98        prot |= PAGE_EXEC;
99    return tlb_set_page_exec(env1, vaddr, paddr, prot, mmu_idx, is_softmmu);
100}
101
102#define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */
103
104#define CODE_GEN_PHYS_HASH_BITS     15
105#define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)
106
107#define MIN_CODE_GEN_BUFFER_SIZE     (1024 * 1024)
108
109/* estimated block size for TB allocation */
110/* XXX: use a per code average code fragment size and modulate it
111   according to the host CPU */
112#if defined(CONFIG_SOFTMMU)
113#define CODE_GEN_AVG_BLOCK_SIZE 128
114#else
115#define CODE_GEN_AVG_BLOCK_SIZE 64
116#endif
117
118#if defined(_ARCH_PPC) || defined(__x86_64__) || defined(__arm__)
119#define USE_DIRECT_JUMP
120#endif
121#if defined(__i386__) && !defined(_WIN32)
122#define USE_DIRECT_JUMP
123#endif
124
125struct TranslationBlock {
126    target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
127    target_ulong cs_base; /* CS base for this block */
128    uint64_t flags; /* flags defining in which context the code was generated */
129    uint16_t size;      /* size of target code for this block (1 <=
130                           size <= TARGET_PAGE_SIZE) */
131    uint16_t cflags;    /* compile flags */
132#define CF_COUNT_MASK  0x7fff
133#define CF_LAST_IO     0x8000 /* Last insn may be an IO access.  */
134
135    uint8_t *tc_ptr;    /* pointer to the translated code */
136    /* next matching tb for physical address. */
137    struct TranslationBlock *phys_hash_next;
138    /* first and second physical page containing code. The lower bit
139       of the pointer tells the index in page_next[] */
140    struct TranslationBlock *page_next[2];
141    target_ulong page_addr[2];
142
143    /* the following data are used to directly call another TB from
144       the code of this one. */
145    uint16_t tb_next_offset[2]; /* offset of original jump target */
146#ifdef USE_DIRECT_JUMP
147    uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
148#else
149    unsigned long tb_next[2]; /* address of jump generated code */
150#endif
151    /* list of TBs jumping to this one. This is a circular list using
152       the two least significant bits of the pointers to tell what is
153       the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
154       jmp_first */
155    struct TranslationBlock *jmp_next[2];
156    struct TranslationBlock *jmp_first;
157#ifdef CONFIG_TRACE
158    struct BBRec *bb_rec;
159    uint64_t prev_time;
160#endif
161
162#ifdef CONFIG_MEMCHECK
163    /* Maps PCs in this translation block to corresponding PCs in guest address
164     * space. The array is arranged in such way, that every even entry contains
165     * PC in the translation block, followed by an odd entry that contains
166     * guest PC corresponding to that PC in the translation block. This
167     * arrangement is set by tcg_gen_code_common that initializes this array
168     * when performing guest code translation. */
169    target_ulong*   tpc2gpc;
170    /* Number of pairs (pc_tb, pc_guest) in tpc2gpc array. */
171    unsigned int    tpc2gpc_pairs;
172#endif  // CONFIG_MEMCHECK
173
174    uint32_t icount;
175};
176
177static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
178{
179    target_ulong tmp;
180    tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
181    return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
182}
183
184static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
185{
186    target_ulong tmp;
187    tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
188    return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
189	    | (tmp & TB_JMP_ADDR_MASK));
190}
191
192static inline unsigned int tb_phys_hash_func(unsigned long pc)
193{
194    return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
195}
196
197#ifdef CONFIG_MEMCHECK
198/* Gets translated PC for a given (translated PC, guest PC) pair.
199 * Return:
200 *  Translated PC, or NULL if pair index was too large.
201 */
202static inline target_ulong
203tb_get_tb_pc(const TranslationBlock* tb, unsigned int pair)
204{
205    return (tb->tpc2gpc != NULL && pair < tb->tpc2gpc_pairs) ?
206                                                    tb->tpc2gpc[pair * 2] : 0;
207}
208
209/* Gets guest PC for a given (translated PC, guest PC) pair.
210 * Return:
211 *  Guest PC, or NULL if pair index was too large.
212 */
213static inline target_ulong
214tb_get_guest_pc(const TranslationBlock* tb, unsigned int pair)
215{
216    return (tb->tpc2gpc != NULL && pair < tb->tpc2gpc_pairs) ?
217            tb->tpc2gpc[pair * 2 + 1] : 0;
218}
219
220/* Gets guest PC for a given translated PC.
221 * Return:
222 *  Guest PC for a given translated PC, or NULL if there was no pair, matching
223 *  translated PC in tb's tpc2gpc array.
224 */
225static inline target_ulong
226tb_search_guest_pc_from_tb_pc(const TranslationBlock* tb, target_ulong tb_pc)
227{
228    if (tb->tpc2gpc != NULL && tb->tpc2gpc_pairs != 0) {
229        unsigned int m_min = 0;
230        unsigned int m_max = (tb->tpc2gpc_pairs - 1) << 1;
231        /* Make sure that tb_pc is within TB array. */
232        if (tb_pc < tb->tpc2gpc[0]) {
233            return 0;
234        }
235        while (m_min <= m_max) {
236            const unsigned int m = ((m_min + m_max) >> 1) & ~1;
237            if (tb_pc < tb->tpc2gpc[m]) {
238                m_max = m - 2;
239            } else if (m == m_max || tb_pc < tb->tpc2gpc[m + 2]) {
240                return tb->tpc2gpc[m + 1];
241            } else {
242                m_min = m + 2;
243            }
244        }
245        return tb->tpc2gpc[m_max + 1];
246    }
247    return 0;
248}
249#endif  // CONFIG_MEMCHECK
250
251TranslationBlock *tb_alloc(target_ulong pc);
252void tb_free(TranslationBlock *tb);
253void tb_flush(CPUState *env);
254void tb_link_phys(TranslationBlock *tb,
255                  target_ulong phys_pc, target_ulong phys_page2);
256void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr);
257
258extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
259extern uint8_t *code_gen_ptr;
260extern int code_gen_max_blocks;
261
262#if defined(USE_DIRECT_JUMP)
263
264#if defined(_ARCH_PPC)
265extern void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr);
266#define tb_set_jmp_target1 ppc_tb_set_jmp_target
267#elif defined(__i386__) || defined(__x86_64__)
268static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
269{
270    /* patch the branch destination */
271    *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
272    /* no need to flush icache explicitly */
273}
274#elif defined(__arm__)
275static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
276{
277#if QEMU_GNUC_PREREQ(4, 1)
278    void __clear_cache(char *beg, char *end);
279#else
280    register unsigned long _beg __asm ("a1");
281    register unsigned long _end __asm ("a2");
282    register unsigned long _flg __asm ("a3");
283#endif
284
285    /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
286    *(uint32_t *)jmp_addr |= ((addr - (jmp_addr + 8)) >> 2) & 0xffffff;
287
288#if QEMU_GNUC_PREREQ(4, 1)
289    __clear_cache((char *) jmp_addr, (char *) jmp_addr + 4);
290#else
291    /* flush icache */
292    _beg = jmp_addr;
293    _end = jmp_addr + 4;
294    _flg = 0;
295    __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
296#endif
297}
298#endif
299
300static inline void tb_set_jmp_target(TranslationBlock *tb,
301                                     int n, unsigned long addr)
302{
303    unsigned long offset;
304
305    offset = tb->tb_jmp_offset[n];
306    tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
307    offset = tb->tb_jmp_offset[n + 2];
308    if (offset != 0xffff)
309        tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
310}
311
312#else
313
314/* set the jump target */
315static inline void tb_set_jmp_target(TranslationBlock *tb,
316                                     int n, unsigned long addr)
317{
318    tb->tb_next[n] = addr;
319}
320
321#endif
322
323static inline void tb_add_jump(TranslationBlock *tb, int n,
324                               TranslationBlock *tb_next)
325{
326    /* NOTE: this test is only needed for thread safety */
327    if (!tb->jmp_next[n]) {
328        /* patch the native jump address */
329        tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
330
331        /* add in TB jmp circular list */
332        tb->jmp_next[n] = tb_next->jmp_first;
333        tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
334    }
335}
336
337TranslationBlock *tb_find_pc(unsigned long pc_ptr);
338
339extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
340extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
341extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
342
343#include "qemu-lock.h"
344
345extern spinlock_t tb_lock;
346
347extern int tb_invalidated_flag;
348
349#if !defined(CONFIG_USER_ONLY)
350
351void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
352              void *retaddr);
353
354#include "softmmu_defs.h"
355
356#define ACCESS_TYPE (NB_MMU_MODES + 1)
357#define MEMSUFFIX _code
358#define env cpu_single_env
359
360#define DATA_SIZE 1
361#include "softmmu_header.h"
362
363#define DATA_SIZE 2
364#include "softmmu_header.h"
365
366#define DATA_SIZE 4
367#include "softmmu_header.h"
368
369#define DATA_SIZE 8
370#include "softmmu_header.h"
371
372#undef ACCESS_TYPE
373#undef MEMSUFFIX
374#undef env
375
376#endif
377
378#if defined(CONFIG_USER_ONLY)
379static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr)
380{
381    return addr;
382}
383#else
384/* NOTE: this function can trigger an exception */
385/* NOTE2: the returned address is not exactly the physical address: it
386   is the offset relative to phys_ram_base */
387static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr)
388{
389    int mmu_idx, page_index, pd;
390    void *p;
391
392    page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
393    mmu_idx = cpu_mmu_index(env1);
394    if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
395                 (addr & TARGET_PAGE_MASK))) {
396        ldub_code(addr);
397    }
398    pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK;
399    if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
400#if defined(TARGET_SPARC) || defined(TARGET_MIPS)
401        do_unassigned_access(addr, 0, 1, 0, 4);
402#else
403        cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
404#endif
405    }
406    p = (void *)(unsigned long)addr
407        + env1->tlb_table[mmu_idx][page_index].addend;
408    return qemu_ram_addr_from_host(p);
409}
410
411/* Deterministic execution requires that IO only be performed on the last
412   instruction of a TB so that interrupts take effect immediately.  */
413static inline int can_do_io(CPUState *env)
414{
415    if (!use_icount)
416        return 1;
417
418    /* If not executing code then assume we are ok.  */
419    if (!env->current_tb)
420        return 1;
421
422    return env->can_do_io != 0;
423}
424#endif
425
426#ifdef CONFIG_KQEMU
427#define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG))
428
429#define MSR_QPI_COMMBASE 0xfabe0010
430
431int kqemu_init(CPUState *env);
432int kqemu_cpu_exec(CPUState *env);
433void kqemu_flush_page(CPUState *env, target_ulong addr);
434void kqemu_flush(CPUState *env, int global);
435void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
436void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
437void kqemu_set_phys_mem(uint64_t start_addr, ram_addr_t size,
438                        ram_addr_t phys_offset);
439void kqemu_cpu_interrupt(CPUState *env);
440void kqemu_record_dump(void);
441
442extern uint32_t kqemu_comm_base;
443
444extern ram_addr_t kqemu_phys_ram_size;
445extern uint8_t *kqemu_phys_ram_base;
446
447static inline int kqemu_is_ok(CPUState *env)
448{
449    return(env->kqemu_enabled &&
450           (env->cr[0] & CR0_PE_MASK) &&
451           !(env->hflags & HF_INHIBIT_IRQ_MASK) &&
452           (env->eflags & IF_MASK) &&
453           !(env->eflags & VM_MASK) &&
454           (env->kqemu_enabled == 2 ||
455            ((env->hflags & HF_CPL_MASK) == 3 &&
456             (env->eflags & IOPL_MASK) != IOPL_MASK)));
457}
458
459#endif
460
461typedef void (CPUDebugExcpHandler)(CPUState *env);
462
463CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler);
464
465/* vl.c */
466extern int singlestep;
467
468#endif
469