1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25/* 26 * DEF(name, oargs, iargs, cargs, flags) 27 */ 28 29/* predefined ops */ 30DEF(end, 0, 0, 0, 0) /* must be kept first */ 31DEF(nop, 0, 0, 0, 0) 32DEF(nop1, 0, 0, 1, 0) 33DEF(nop2, 0, 0, 2, 0) 34DEF(nop3, 0, 0, 3, 0) 35DEF(nopn, 0, 0, 1, 0) /* variable number of parameters */ 36 37DEF(discard, 1, 0, 0, 0) 38 39DEF(set_label, 0, 0, 1, 0) 40DEF(call, 0, 1, 2, TCG_OPF_SIDE_EFFECTS) /* variable number of parameters */ 41DEF(jmp, 0, 1, 0, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) 42DEF(br, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) 43 44DEF(mov_i32, 1, 1, 0, 0) 45DEF(movi_i32, 1, 0, 1, 0) 46DEF(setcond_i32, 1, 2, 1, 0) 47/* load/store */ 48DEF(ld8u_i32, 1, 1, 1, 0) 49DEF(ld8s_i32, 1, 1, 1, 0) 50DEF(ld16u_i32, 1, 1, 1, 0) 51DEF(ld16s_i32, 1, 1, 1, 0) 52DEF(ld_i32, 1, 1, 1, 0) 53DEF(st8_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) 54DEF(st16_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) 55DEF(st_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) 56/* arith */ 57DEF(add_i32, 1, 2, 0, 0) 58DEF(sub_i32, 1, 2, 0, 0) 59DEF(mul_i32, 1, 2, 0, 0) 60#ifdef TCG_TARGET_HAS_div_i32 61DEF(div_i32, 1, 2, 0, 0) 62DEF(divu_i32, 1, 2, 0, 0) 63DEF(rem_i32, 1, 2, 0, 0) 64DEF(remu_i32, 1, 2, 0, 0) 65#endif 66#ifdef TCG_TARGET_HAS_div2_i32 67DEF(div2_i32, 2, 3, 0, 0) 68DEF(divu2_i32, 2, 3, 0, 0) 69#endif 70DEF(and_i32, 1, 2, 0, 0) 71DEF(or_i32, 1, 2, 0, 0) 72DEF(xor_i32, 1, 2, 0, 0) 73/* shifts/rotates */ 74DEF(shl_i32, 1, 2, 0, 0) 75DEF(shr_i32, 1, 2, 0, 0) 76DEF(sar_i32, 1, 2, 0, 0) 77#ifdef TCG_TARGET_HAS_rot_i32 78DEF(rotl_i32, 1, 2, 0, 0) 79DEF(rotr_i32, 1, 2, 0, 0) 80#endif 81#ifdef TCG_TARGET_HAS_deposit_i32 82DEF(deposit_i32, 1, 2, 2, 0) 83#endif 84 85DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) 86#if TCG_TARGET_REG_BITS == 32 87DEF(add2_i32, 2, 4, 0, 0) 88DEF(sub2_i32, 2, 4, 0, 0) 89DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) 90DEF(mulu2_i32, 2, 2, 0, 0) 91DEF(setcond2_i32, 1, 4, 1, 0) 92#endif 93#ifdef TCG_TARGET_HAS_ext8s_i32 94DEF(ext8s_i32, 1, 1, 0, 0) 95#endif 96#ifdef TCG_TARGET_HAS_ext16s_i32 97DEF(ext16s_i32, 1, 1, 0, 0) 98#endif 99#ifdef TCG_TARGET_HAS_ext8u_i32 100DEF(ext8u_i32, 1, 1, 0, 0) 101#endif 102#ifdef TCG_TARGET_HAS_ext16u_i32 103DEF(ext16u_i32, 1, 1, 0, 0) 104#endif 105#ifdef TCG_TARGET_HAS_bswap16_i32 106DEF(bswap16_i32, 1, 1, 0, 0) 107#endif 108#ifdef TCG_TARGET_HAS_bswap32_i32 109DEF(bswap32_i32, 1, 1, 0, 0) 110#endif 111#ifdef TCG_TARGET_HAS_not_i32 112DEF(not_i32, 1, 1, 0, 0) 113#endif 114#ifdef TCG_TARGET_HAS_neg_i32 115DEF(neg_i32, 1, 1, 0, 0) 116#endif 117#ifdef TCG_TARGET_HAS_andc_i32 118DEF(andc_i32, 1, 2, 0, 0) 119#endif 120#ifdef TCG_TARGET_HAS_orc_i32 121DEF(orc_i32, 1, 2, 0, 0) 122#endif 123#ifdef TCG_TARGET_HAS_eqv_i32 124DEF(eqv_i32, 1, 2, 0, 0) 125#endif 126#ifdef TCG_TARGET_HAS_nand_i32 127DEF(nand_i32, 1, 2, 0, 0) 128#endif 129#ifdef TCG_TARGET_HAS_nor_i32 130DEF(nor_i32, 1, 2, 0, 0) 131#endif 132 133#if TCG_TARGET_REG_BITS == 64 134DEF(mov_i64, 1, 1, 0, 0) 135DEF(movi_i64, 1, 0, 1, 0) 136DEF(setcond_i64, 1, 2, 1, 0) 137/* load/store */ 138DEF(ld8u_i64, 1, 1, 1, 0) 139DEF(ld8s_i64, 1, 1, 1, 0) 140DEF(ld16u_i64, 1, 1, 1, 0) 141DEF(ld16s_i64, 1, 1, 1, 0) 142DEF(ld32u_i64, 1, 1, 1, 0) 143DEF(ld32s_i64, 1, 1, 1, 0) 144DEF(ld_i64, 1, 1, 1, 0) 145DEF(st8_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) 146DEF(st16_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) 147DEF(st32_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) 148DEF(st_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) 149/* arith */ 150DEF(add_i64, 1, 2, 0, 0) 151DEF(sub_i64, 1, 2, 0, 0) 152DEF(mul_i64, 1, 2, 0, 0) 153#ifdef TCG_TARGET_HAS_div_i64 154DEF(div_i64, 1, 2, 0, 0) 155DEF(divu_i64, 1, 2, 0, 0) 156DEF(rem_i64, 1, 2, 0, 0) 157DEF(remu_i64, 1, 2, 0, 0) 158#endif 159#ifdef TCG_TARGET_HAS_div2_i64 160DEF(div2_i64, 2, 3, 0, 0) 161DEF(divu2_i64, 2, 3, 0, 0) 162#endif 163DEF(and_i64, 1, 2, 0, 0) 164DEF(or_i64, 1, 2, 0, 0) 165DEF(xor_i64, 1, 2, 0, 0) 166/* shifts/rotates */ 167DEF(shl_i64, 1, 2, 0, 0) 168DEF(shr_i64, 1, 2, 0, 0) 169DEF(sar_i64, 1, 2, 0, 0) 170#ifdef TCG_TARGET_HAS_rot_i64 171DEF(rotl_i64, 1, 2, 0, 0) 172DEF(rotr_i64, 1, 2, 0, 0) 173#endif 174#ifdef TCG_TARGET_HAS_deposit_i64 175DEF(deposit_i64, 1, 2, 2, 0) 176#endif 177 178DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) 179#ifdef TCG_TARGET_HAS_ext8s_i64 180DEF(ext8s_i64, 1, 1, 0, 0) 181#endif 182#ifdef TCG_TARGET_HAS_ext16s_i64 183DEF(ext16s_i64, 1, 1, 0, 0) 184#endif 185#ifdef TCG_TARGET_HAS_ext32s_i64 186DEF(ext32s_i64, 1, 1, 0, 0) 187#endif 188#ifdef TCG_TARGET_HAS_ext8u_i64 189DEF(ext8u_i64, 1, 1, 0, 0) 190#endif 191#ifdef TCG_TARGET_HAS_ext16u_i64 192DEF(ext16u_i64, 1, 1, 0, 0) 193#endif 194#ifdef TCG_TARGET_HAS_ext32u_i64 195DEF(ext32u_i64, 1, 1, 0, 0) 196#endif 197#ifdef TCG_TARGET_HAS_bswap16_i64 198DEF(bswap16_i64, 1, 1, 0, 0) 199#endif 200#ifdef TCG_TARGET_HAS_bswap32_i64 201DEF(bswap32_i64, 1, 1, 0, 0) 202#endif 203#ifdef TCG_TARGET_HAS_bswap64_i64 204DEF(bswap64_i64, 1, 1, 0, 0) 205#endif 206#ifdef TCG_TARGET_HAS_not_i64 207DEF(not_i64, 1, 1, 0, 0) 208#endif 209#ifdef TCG_TARGET_HAS_neg_i64 210DEF(neg_i64, 1, 1, 0, 0) 211#endif 212#ifdef TCG_TARGET_HAS_andc_i64 213DEF(andc_i64, 1, 2, 0, 0) 214#endif 215#ifdef TCG_TARGET_HAS_orc_i64 216DEF(orc_i64, 1, 2, 0, 0) 217#endif 218#ifdef TCG_TARGET_HAS_eqv_i64 219DEF(eqv_i64, 1, 2, 0, 0) 220#endif 221#ifdef TCG_TARGET_HAS_nand_i64 222DEF(nand_i64, 1, 2, 0, 0) 223#endif 224#ifdef TCG_TARGET_HAS_nor_i64 225DEF(nor_i64, 1, 2, 0, 0) 226#endif 227#endif 228 229/* QEMU specific */ 230#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS 231DEF(debug_insn_start, 0, 0, 2, 0) 232#else 233DEF(debug_insn_start, 0, 0, 1, 0) 234#endif 235DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) 236DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) 237/* Note: even if TARGET_LONG_BITS is not defined, the INDEX_op 238 constants must be defined */ 239#if TCG_TARGET_REG_BITS == 32 240#if TARGET_LONG_BITS == 32 241DEF(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 242#else 243DEF(qemu_ld8u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 244#endif 245#if TARGET_LONG_BITS == 32 246DEF(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 247#else 248DEF(qemu_ld8s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 249#endif 250#if TARGET_LONG_BITS == 32 251DEF(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 252#else 253DEF(qemu_ld16u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 254#endif 255#if TARGET_LONG_BITS == 32 256DEF(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 257#else 258DEF(qemu_ld16s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 259#endif 260#if TARGET_LONG_BITS == 32 261DEF(qemu_ld32, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 262#else 263DEF(qemu_ld32, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 264#endif 265#if TARGET_LONG_BITS == 32 266DEF(qemu_ld32s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 267#else 268DEF(qemu_ld32s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 269#endif 270#if TARGET_LONG_BITS == 32 271DEF(qemu_ld64, 2, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 272#else 273DEF(qemu_ld64, 2, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 274#endif 275 276#if TARGET_LONG_BITS == 32 277DEF(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 278#else 279DEF(qemu_st8, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 280#endif 281#if TARGET_LONG_BITS == 32 282DEF(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 283#else 284DEF(qemu_st16, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 285#endif 286#if TARGET_LONG_BITS == 32 287DEF(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 288#else 289DEF(qemu_st32, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 290#endif 291#if TARGET_LONG_BITS == 32 292DEF(qemu_st64, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 293#else 294DEF(qemu_st64, 0, 4, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 295#endif 296 297#else /* TCG_TARGET_REG_BITS == 32 */ 298 299DEF(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 300DEF(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 301DEF(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 302DEF(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 303DEF(qemu_ld32, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 304DEF(qemu_ld32u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 305DEF(qemu_ld32s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 306DEF(qemu_ld64, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 307 308DEF(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 309DEF(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 310DEF(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 311DEF(qemu_st64, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 312 313#endif /* TCG_TARGET_REG_BITS != 32 */ 314 315#undef DEF 316