Cross Reference: /external/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp

Lines Matching defs:NumVecs
203   /// SelectVLD - Select NEON load intrinsics.  NumVecs should be
206   /// For NumVecs <= 2, QOpcodes1 is not used.
207   SDNode *SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
211   /// SelectVST - Select NEON store intrinsics.  NumVecs should
214   /// For NumVecs <= 2, QOpcodes1 is not used.
215   SDNode *SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
219   /// SelectVLDSTLane - Select NEON load/store lane intrinsics.  NumVecs should
223                           bool isUpdating, unsigned NumVecs,
226   /// SelectVLDDup - Select NEON load-duplicate intrinsics.  NumVecs
229   SDNode *SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs,
232   /// SelectVTBL - Select NEON VTBL and VTBX intrinsics.  NumVecs should be 2,
235   SDNode *SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
279   SDValue GetVLDSTAlign(SDValue Align, unsigned NumVecs, bool is64BitVector);
1526 SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, unsigned NumVecs,
1528   unsigned NumRegs = NumVecs;
1529   if (!is64BitVector && NumVecs < 3)
1591 SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
1595   assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");
1606   Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1623     assert(NumVecs == 1 && "v2i64 type only supported for VLD1");
1628   if (NumVecs == 1)
1631     unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1648   if (is64BitVector || NumVecs <= 2) {
1657       if ((NumVecs == 1 || NumVecs == 2) && !isa<ConstantSDNode>(Inc.getNode()))
1661       if ((NumVecs != 1 && NumVecs != 2 && Opc != ARM::VLD1q64wb_fixed) ||
1707   if (NumVecs == 1)
1715   for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1718   ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));
1720     ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLd, 2));
1724 SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
1728   assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");
1743   Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1760     assert(NumVecs == 1 && "v2i64 type only supported for VST1");
1774   if (is64BitVector || NumVecs <= 2) {
1776     if (NumVecs == 1) {
1782       if (NumVecs == 2)
1788         SDValue V3 = (NumVecs == 3)
1808       if (NumVecs <= 2 && !isa<ConstantSDNode>(Inc.getNode()))
1812       if ((NumVecs > 2 && Opc != ARM::VST1q64wb_fixed) ||
1836   SDValue V3 = (NumVecs == 3)
1871                                          bool isUpdating, unsigned NumVecs,
1874   assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
1888     cast<ConstantSDNode>(N->getOperand(Vec0Idx + NumVecs))->getZExtValue();
1893   if (NumVecs != 3) {
1895     unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
1923     unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1947   if (NumVecs == 2) {
1954     SDValue V3 = (NumVecs == 3)
1981   for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1984   ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, 1));
1986     ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdLn, 2));
1991                                       unsigned NumVecs,
1993   assert(NumVecs >=2 && NumVecs <= 4 && "VLDDup NumVecs out-of-range");
2007   if (NumVecs != 3) {
2009     unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
2044     else if (NumVecs > 2)
2051   unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
2065   for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
2068   ReplaceUses(SDValue(N, NumVecs), SDValue(VLdDup, 1));
2070     ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdDup, 2));
2074 SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs,
2076   assert(NumVecs >= 2 && NumVecs <= 4 && "VTBL NumVecs out-of-range");
2085   if (NumVecs == 2)
2091     SDValue V3 = (NumVecs == 3)
2101   Ops.push_back(N->getOperand(FirstTblReg + NumVecs));