Lines Matching refs:Operands
227 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
257 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
263 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
267 const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
269 return getMCInstOperandNumImpl(Kind, Inst, Operands, OperandNum, NumMCOperands);
2519 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2542 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2599 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2603 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2617 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2623 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
2627 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2653 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2702 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2730 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
2739 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2750 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
2758 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2769 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
2776 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2803 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
2854 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2967 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
2971 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3029 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3048 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3052 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3056 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3073 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3079 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3083 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3253 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3265 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3270 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3281 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3337 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3343 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3371 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3377 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3436 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3499 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3504 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
3545 Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
3551 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3568 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
3580 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3641 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
3650 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3690 Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
3696 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3758 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
3764 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3804 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
3811 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3847 Operands.push_back(
3875 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
3886 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3888 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3889 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3893 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3895 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3903 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3907 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3908 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3910 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3912 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3920 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3921 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3926 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3927 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3935 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3938 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3939 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3940 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3948 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3949 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3954 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3955 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3963 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3964 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3969 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3970 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3979 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3982 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3983 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3984 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3992 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3995 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3996 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3997 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4005 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4008 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4009 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
4010 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4018 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4020 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4024 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4026 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
4028 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4036 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4038 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4042 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4044 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
4046 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4054 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4058 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4060 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4062 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
4064 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4072 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4076 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4078 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4080 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
4082 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4090 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4092 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4093 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4097 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
4099 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4107 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4111 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4112 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4114 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
4116 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4124 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4125 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4128 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
4129 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4137 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4138 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4139 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
4143 if (Operands.size() == 6 &&
4144 ((ARMOperand*)Operands[4])->getReg() ==
4145 ((ARMOperand*)Operands[3])->getReg())
4147 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
4149 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
4154 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4156 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4160 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4162 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4167 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4169 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4173 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4175 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
4177 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4182 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4186 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4188 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4190 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4195 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4199 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4201 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
4203 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4205 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4211 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4232 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
4238 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4284 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
4291 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4333 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4340 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4377 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
4384 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4450 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4476 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
4497 Operands.push_back(ARMOperand::CreateImm(
4513 Operands.push_back(ARMOperand::CreateImm(
4525 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4531 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4545 if (!tryParseRegisterWithWriteBack(Operands))
4547 int Res = tryParseShiftRegister(Operands);
4557 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4575 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4579 return parseMemory(Operands);
4581 return parseRegisterList(Operands);
4600 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4621 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4807 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4819 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
4820 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
4821 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
4822 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4827 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
4828 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4829 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4830 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4838 Operands.size() == 6 &&
4839 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4840 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4841 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
4842 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4843 ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) ||
4844 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
4852 Operands.size() == 6 &&
4853 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4854 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4855 static_cast<ARMOperand*>(Operands[5])->isImm()) {
4862 if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4863 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) &&
4864 static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
4865 static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
4870 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
4871 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
4872 static_cast<ARMOperand*>(Operands[5])->isImm0_7())
4883 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
4884 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4885 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4886 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4887 static_cast<ARMOperand*>(Operands[5])->isReg() &&
4892 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4893 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4894 !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
4896 (static_cast<ARMOperand*>(Operands[3])->getReg() !=
4897 static_cast<ARMOperand*>(Operands[5])->getReg() &&
4898 static_cast<ARMOperand*>(Operands[3])->getReg() !=
4899 static_cast<ARMOperand*>(Operands[4])->getReg())))
4904 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
4905 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4906 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4907 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4911 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4912 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4924 (Operands.size() == 5 || Operands.size() == 6) &&
4925 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4926 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
4927 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4928 (static_cast<ARMOperand*>(Operands[4])->isImm() ||
4929 (Operands.size() == 6 &&
4930 static_cast<ARMOperand*>(Operands[5])->isImm())))
4955 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4991 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5015 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5049 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5057 Operands.push_back(ARMOperand::CreateCondCode(
5063 Operands.push_back(ARMOperand::CreateImm(
5082 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5089 if (parseOperand(Operands, Mnemonic)) {
5098 if (parseOperand(Operands, Mnemonic)) {
5120 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
5121 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5122 Operands.erase(Operands.begin() + 1);
5131 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5132 static_cast<ARMOperand*>(Operands[2])->isImm()) {
5133 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5134 Operands.erase(Operands.begin() + 1);
5142 Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
5143 static_cast<ARMOperand*>(Operands[5])->isImm()) {
5144 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
5147 Operands.erase(Operands.begin() + 5);
5148 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
5153 if ((Mnemonic == "vcmp" || Mnemonic == "vcmpe") && Operands.size() == 5 &&
5154 static_cast<ARMOperand*>(Operands[4])->isImm()) {
5155 ARMOperand *Op = static_cast<ARMOperand*>(Operands[4]);
5158 Operands.erase(Operands.begin() + 4);
5159 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
5166 if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 &&
5167 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5168 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5169 static_cast<ARMOperand*>(Operands[5])->isImm()) {
5170 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
5177 (isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
5178 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()))))){
5179 Operands.erase(Operands.begin() + 5);
5180 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
5231 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5233 SMLoc Loc = Operands[0]->getStartLoc();
5254 for (unsigned i = 1; i < Operands.size(); ++i)
5255 if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
5256 CondLoc = Operands[i]->getStartLoc();
5278 return Error(Operands[3]->getStartLoc(),
5287 return Error(Operands[3]->getStartLoc(),
5298 return Error(Operands[3]->getStartLoc(),
5308 return Error(Operands[5]->getStartLoc(),
5322 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5323 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
5326 return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
5330 return Error(Operands[2]->getStartLoc(),
5335 return Error(Operands[3]->getStartLoc(),
5343 return Error(Operands[4]->getStartLoc(),
5357 if (Operands.size() == 6 &&
5358 (((ARMOperand*)Operands[3])->getReg() !=
5359 ((ARMOperand*)Operands[5])->getReg()) &&
5360 (((ARMOperand*)Operands[3])->getReg() !=
5361 ((ARMOperand*)Operands[4])->getReg())) {
5362 return Error(Operands[3]->getStartLoc(),
5374 return Error(Operands[2]->getStartLoc(),
5382 return Error(Operands[2]->getStartLoc(),
5389 return Error(Operands[4]->getStartLoc(),
5398 return Error(Operands[4]->getStartLoc(),
5666 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
6757 !(static_cast<ARMOperand*>(Operands[3])->isToken() &&
6758 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) {
6961 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
6979 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
6995 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" ||
7004 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||
7015 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7025 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7041 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7042 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7063 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7064 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7121 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7122 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
7186 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7187 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7208 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7209 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7231 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7232 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7346 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7347 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7385 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7386 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7462 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
7469 MatchResult = MatchInstructionImpl(Operands, Kind, Inst, ErrorInfo);
7475 if (validateInstruction(Inst, Operands)) {
7486 while (processInstruction(Inst, Operands))
7520 if (ErrorInfo >= Operands.size())
7523 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7531 ((ARMOperand*)Operands[0])->getLocRange());
7541 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();