Lines Matching defs:OpNo
69 unsigned getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
75 unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
83 unsigned getMemEncoding(const MCInst &MI, unsigned OpNo,
85 unsigned getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
87 unsigned getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
142 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
145 const MCOperand &MO = MI.getOperand(OpNo);
162 getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
165 const MCOperand &MO = MI.getOperand(OpNo);
282 MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
285 assert(MI.getOperand(OpNo).isReg());
286 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups) << 16;
287 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups);
293 MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
295 assert(MI.getOperand(OpNo).isImm());
296 unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups);
303 MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
305 assert(MI.getOperand(OpNo-1).isImm());
306 assert(MI.getOperand(OpNo).isImm());
307 unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups);
308 unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups);