Cross Reference: /external/llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Lines Matching defs:RHS
886     // (for better address arithmetic) if the LHS and RHS of the OR are provably
896       // If all of the bits are known zero on the LHS or RHS, the add won't
947       // (for better address arithmetic) if the LHS and RHS of the OR are
953         // If all of the bits are known zero on the LHS or RHS, the add won't
1060       // (for better address arithmetic) if the LHS and RHS of the OR are
1065         // If all of the bits are known zero on the LHS or RHS, the add won't
3720   SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3724   // If the RHS of the comparison is a 0.0, we don't need to do the
3726   if (isFloatingPointZero(RHS))
3753     Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
3759     Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
3765     Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
3771     Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
4050 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
4055                      DAG.getConstant(IID, MVT::i32), LHS, RHS);
4071 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
4073   // Force LHS/RHS to be the right type.
4075   RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
4080   SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
4235     SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
4236     LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS);
4242     SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
4243     LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS);
4253                                       SDValue RHS, SelectionDAG &DAG,
4275     return RHS;
4279   OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
4280   OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
4517     Op.getOperand(3),  // RHS
4585     SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4590     SDValue RHSSwap =   // = vrlw RHS, 16
4591       BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
4595     RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
4601                                         LHS, RHS, DAG, dl, MVT::v4i32);
4610     SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4615                             LHS, RHS, Zero, DAG, dl);
4617     SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4621                                            LHS, RHS, DAG, dl, MVT::v8i16);
4626                                           LHS, RHS, DAG, dl, MVT::v8i16);
5555     SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
5560         isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
5566       unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
5581         LHS.getOperand(3),  // RHS of compare