Lines Matching defs:imm
867 /// can be more efficiently represented with [r+imm].
871 short imm = 0;
873 if (isIntS16Immediate(N.getOperand(1), imm))
882 if (isIntS16Immediate(N.getOperand(1), imm))
910 /// a signed 16-bit displacement [r+imm], and if it is not better
922 short imm = 0;
923 if (isIntS16Immediate(N.getOperand(1), imm)) {
924 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
944 short imm = 0;
945 if (isIntS16Immediate(N.getOperand(1), imm)) {
952 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
956 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
1003 // reg+imm, e.g. where imm = 0.
1025 /// [r+imm*4]. Suitable for use by STD and friends.
1036 short imm = 0;
1037 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
1038 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
1057 short imm = 0;
1058 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
1064 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1068 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
1139 // LDU/STU use reg+imm*4, others use reg+imm.
1141 // reg + imm
1145 // reg + imm * 4.