Lines Matching refs:RB
723 /* The RB field in an X, XO, M, or MDS form instruction. */
724 #define RB RAOPT + 1
728 /* The RB field in an X form instruction when it must be the same as
731 #define RBS RB + 1
1454 /* The RB field in an X form instruction when it must be the same as
1760 /* An X_MASK with the RB field fixed. */
1769 /* An X_MASK with the RA and RB fields fixed. */
1864 /* An XO_MASK with the RB field fixed. */
2063 { "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2064 { "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2065 { "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2066 { "macchwo.", XO(4,172,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2067 { "macchws", XO(4,236,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2068 { "macchws.", XO(4,236,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2069 { "macchwso", XO(4,236,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2070 { "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2071 { "macchwsu", XO(4,204,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2072 { "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2073 { "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2074 { "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2075 { "macchwu", XO(4,140,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2076 { "macchwu.", XO(4,140,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2077 { "macchwuo", XO(4,140,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2078 { "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2079 { "machhw", XO(4,44,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2080 { "machhw.", XO(4,44,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2081 { "machhwo", XO(4,44,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2082 { "machhwo.", XO(4,44,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2083 { "machhws", XO(4,108,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2084 { "machhws.", XO(4,108,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2085 { "machhwso", XO(4,108,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2086 { "machhwso.", XO(4,108,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2087 { "machhwsu", XO(4,76,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2088 { "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2089 { "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2090 { "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2091 { "machhwu", XO(4,12,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2092 { "machhwu.", XO(4,12,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2093 { "machhwuo", XO(4,12,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2094 { "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2095 { "maclhw", XO(4,428,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2096 { "maclhw.", XO(4,428,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2097 { "maclhwo", XO(4,428,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2098 { "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2099 { "maclhws", XO(4,492,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2100 { "maclhws.", XO(4,492,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2101 { "maclhwso", XO(4,492,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2102 { "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2103 { "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2104 { "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2105 { "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2106 { "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2107 { "maclhwu", XO(4,396,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2108 { "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2109 { "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2110 { "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2111 { "mulchw", XRC(4,168,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2112 { "mulchw.", XRC(4,168,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2113 { "mulchwu", XRC(4,136,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2114 { "mulchwu.", XRC(4,136,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2115 { "mulhhw", XRC(4,40,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2116 { "mulhhw.", XRC(4,40,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2117 { "mulhhwu", XRC(4,8,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2118 { "mulhhwu.", XRC(4,8,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2119 { "mullhw", XRC(4,424,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2120 { "mullhw.", XRC(4,424,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2121 { "mullhwu", XRC(4,392,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2122 { "mullhwu.", XRC(4,392,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2123 { "nmacchw", XO(4,174,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2124 { "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2125 { "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2126 { "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2127 { "nmacchws", XO(4,238,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2128 { "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2129 { "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2130 { "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2131 { "nmachhw", XO(4,46,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2132 { "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2133 { "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2134 { "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2135 { "nmachhws", XO(4,110,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2136 { "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2137 { "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2138 { "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2139 { "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2140 { "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2141 { "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2142 { "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2143 { "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2144 { "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2145 { "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2146 { "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2153 { "efscfd", VX(4, 719), VX_MASK, PPCEFS, { RS, RB } },
2157 { "efdadd", VX(4, 736), VX_MASK, PPCEFS, { RS, RA, RB } },
2158 { "efdsub", VX(4, 737), VX_MASK, PPCEFS, { RS, RA, RB } },
2159 { "efdmul", VX(4, 744), VX_MASK, PPCEFS, { RS, RA, RB } },
2160 { "efddiv", VX(4, 745), VX_MASK, PPCEFS, { RS, RA, RB } },
2161 { "efdcmpgt", VX(4, 748), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2162 { "efdcmplt", VX(4, 749), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2163 { "efdcmpeq", VX(4, 750), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2164 { "efdtstgt", VX(4, 764), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2165 { "efdtstlt", VX(4, 765), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2166 { "efdtsteq", VX(4, 766), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2167 { "efdcfsi", VX(4, 753), VX_MASK, PPCEFS, { RS, RB } },
2168 { "efdcfsid", VX(4, 739), VX_MASK, PPCEFS, { RS, RB } },
2169 { "efdcfui", VX(4, 752), VX_MASK, PPCEFS, { RS, RB } },
2170 { "efdcfuid", VX(4, 738), VX_MASK, PPCEFS, { RS, RB } },
2171 { "efdcfsf", VX(4, 755), VX_MASK, PPCEFS, { RS, RB } },
2172 { "efdcfuf", VX(4, 754), VX_MASK, PPCEFS, { RS, RB } },
2173 { "efdctsi", VX(4, 757), VX_MASK, PPCEFS, { RS, RB } },
2174 { "efdctsidz",VX(4, 747), VX_MASK, PPCEFS, { RS, RB } },
2175 { "efdctsiz", VX(4, 762), VX_MASK, PPCEFS, { RS, RB } },
2176 { "efdctui", VX(4, 756), VX_MASK, PPCEFS, { RS, RB } },
2177 { "efdctuidz",VX(4, 746), VX_MASK, PPCEFS, { RS, RB } },
2178 { "efdctuiz", VX(4, 760), VX_MASK, PPCEFS, { RS, RB } },
2179 { "efdctsf", VX(4, 759), VX_MASK, PPCEFS, { RS, RB } },
2180 { "efdctuf", VX(4, 758), VX_MASK, PPCEFS, { RS, RB } },
2181 { "efdcfs", VX(4, 751), VX_MASK, PPCEFS, { RS, RB } },
2340 { "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } },
2341 { "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2342 { "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } },
2343 { "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } },
2344 { "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } },
2345 { "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2354 { "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } },
2356 { "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } },
2357 { "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } },
2359 { "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } },
2360 { "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } },
2361 { "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } },
2362 { "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } },
2363 { "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } },
2365 { "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } },
2367 { "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } },
2369 { "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } },
2371 { "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } },
2372 { "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } },
2377 { "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } },
2378 { "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } },
2379 { "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } },
2380 { "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } },
2382 { "evcmpgts", VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2383 { "evcmpgtu", VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2384 { "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2385 { "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2386 { "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2387 { "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } },
2390 { "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } },
2392 { "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } },
2394 { "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } },
2396 { "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } },
2398 { "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } },
2400 { "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } },
2402 { "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } },
2404 { "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } },
2406 { "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } },
2408 { "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } },
2410 { "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } },
2413 { "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } },
2415 { "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } },
2417 { "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } },
2419 { "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } },
2421 { "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } },
2423 { "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } },
2425 { "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } },
2430 { "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } },
2431 { "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } },
2432 { "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } },
2433 { "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } },
2434 { "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2435 { "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2436 { "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2437 { "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2438 { "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2439 { "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2440 { "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } },
2441 { "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } },
2442 { "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } },
2443 { "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } },
2444 { "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } },
2445 { "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } },
2446 { "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } },
2447 { "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } },
2448 { "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } },
2449 { "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } },
2454 { "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } },
2455 { "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } },
2456 { "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } },
2457 { "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } },
2458 { "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2459 { "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2460 { "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2461 { "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2462 { "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2463 { "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2464 { "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB } },
2465 { "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB } },
2466 { "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB } },
2467 { "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB } },
2468 { "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB } },
2469 { "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB } },
2470 { "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB } },
2471 { "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB } },
2472 { "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB } },
2473 { "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB } },
2475 { "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } },
2476 { "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } },
2477 { "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } },
2478 { "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } },
2479 { "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } },
2480 { "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } },
2481 { "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } },
2482 { "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } },
2483 { "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } },
2484 { "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } },
2485 { "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } },
2486 { "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } },
2487 { "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } },
2488 { "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } },
2489 { "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } },
2490 { "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } },
2492 { "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } },
2493 { "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } },
2494 { "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } },
2495 { "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } },
2496 { "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } },
2497 { "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } },
2498 { "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } },
2499 { "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } },
2500 { "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } },
2501 { "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } },
2502 { "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } },
2503 { "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } },
2505 { "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } },
2506 { "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } },
2507 { "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } },
2508 { "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } },
2509 { "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } },
2510 { "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } },
2511 { "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } },
2512 { "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } },
2513 { "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } },
2514 { "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } },
2515 { "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } },
2516 { "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } },
2518 { "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } },
2519 { "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } },
2520 { "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } },
2521 { "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } },
2522 { "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } },
2523 { "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } },
2525 { "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } },
2526 { "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } },
2527 { "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } },
2528 { "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } },
2529 { "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } },
2530 { "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } },
2532 { "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } },
2533 { "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } },
2534 { "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } },
2535 { "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } },
2536 { "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } },
2537 { "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } },
2538 { "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } },
2539 { "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } },
2541 { "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } },
2542 { "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } },
2544 { "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } },
2545 { "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } },
2546 { "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } },
2547 { "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } },
2549 { "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } },
2550 { "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } },
2551 { "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } },
2552 { "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } },
2554 { "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } },
2555 { "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } },
2556 { "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } },
2557 { "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } },
2558 { "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } },
2559 { "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } },
2560 { "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } },
2561 { "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } },
2563 { "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } },
2564 { "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } },
2565 { "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } },
2566 { "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } },
2568 { "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } },
2569 { "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } },
2570 { "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } },
2571 { "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } },
2585 { "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } },
2586 { "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } },
3341 { "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3342 { "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3349 { "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3350 { "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3351 { "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3352 { "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3353 { "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3354 { "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3391 { "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } },
3392 { "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3393 { "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } },
3394 { "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3396 { "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3397 { "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3399 { "cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3400 { "cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3401 { "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } },
3402 { "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3404 { "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } },
3405 { "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } },
3406 { "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } },
3407 { "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } },
3408 { "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } },
3409 { "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } },
3410 { "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } },
3411 { "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } },
3412 { "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } },
3413 { "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } },
3414 { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
3415 { "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
3416 { "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } },
3417 { "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } },
3418 { "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } },
3419 { "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } },
3420 { "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } },
3421 { "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } },
3422 { "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } },
3423 { "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } },
3424 { "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } },
3425 { "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } },
3426 { "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } },
3427 { "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } },
3428 { "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } },
3429 { "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } },
3430 { "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } },
3431 { "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } },
3433 { "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } },
3434 { "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } },
3436 { "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3437 { "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3438 { "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
3439 { "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3440 { "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3441 { "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } },
3442 { "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3443 { "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3444 { "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
3445 { "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3446 { "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3447 { "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
3449 { "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3450 { "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3452 { "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3453 { "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3454 { "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3455 { "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3456 { "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3457 { "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3458 { "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3459 { "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3461 { "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
3462 { "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
3464 { "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB } },
3465 { "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB } },
3466 { "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } },
3467 { "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } },
3473 { "lwarx", X(31,20), XEH_MASK, PPC, { RT, RA0, RB, EH } },
3475 { "ldx", X(31,21), X_MASK, PPC64, { RT, RA0, RB } },
3477 { "icbt", X(31,22), X_MASK, BOOKE|PPCE300, { CT, RA, RB } },
3478 { "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
3480 { "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA0, RB } },
3481 { "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } },
3483 { "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } },
3484 { "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } },
3485 { "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } },
3486 { "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } },
3493 { "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } },
3494 { "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } },
3496 { "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } },
3497 { "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } },
3499 { "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } },
3500 { "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } },
3502 { "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } },
3504 { "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA0, RB } },
3506 { "cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3507 { "cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3508 { "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } },
3509 { "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3511 { "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
3512 { "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
3513 { "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
3514 { "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
3515 { "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
3516 { "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
3517 { "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
3518 { "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
3520 { "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } },
3522 { "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
3524 { "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } },
3525 { "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } },
3527 { "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } },
3529 { "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } },
3534 { "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } },
3535 { "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } },
3537 { "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } },
3538 { "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } },
3539 { "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } },
3540 { "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } },
3541 { "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } },
3542 { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
3543 { "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } },
3544 { "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } },
3545 { "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } },
3546 { "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } },
3547 { "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } },
3548 { "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } },
3549 { "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } },
3550 { "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } },
3551 { "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } },
3553 { "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3554 { "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3556 { "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
3557 { "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
3559 { "dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3560 { "dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3566 { "ldarx", X(31,84), XEH_MASK, PPC64, { RT, RA0, RB, EH } },
3568 { "dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, { RA, RB } },
3569 { "dcbf", X(31,86), XLRT_MASK, PPC, { RA, RB, L } },
3571 { "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB } },
3573 { "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } },
3575 { "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA0, RB } },
3582 { "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } },
3583 { "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } },
3584 { "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } },
3585 { "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } },
3587 { "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } },
3589 { "clf", X(31,118), XTO_MASK, POWER, { RA, RB } },
3591 { "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } },
3596 { "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
3598 { "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } },
3600 { "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA0, RB } },
3602 { "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } },
3606 { "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }},
3608 { "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3609 { "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3610 { "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3611 { "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3612 { "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3613 { "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3614 { "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3615 { "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3617 { "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3618 { "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3619 { "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3620 { "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3621 { "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3622 { "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3623 { "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3624 { "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3626 { "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }},
3634 { "stdx", X(31,149), X_MASK, PPC64, { RS, RA0, RB } },
3636 { "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA0, RB } },
3638 { "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA0, RB } },
3639 { "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } },
3641 { "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA0, RB } },
3643 { "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA0, RB } },
3645 { "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } },
3646 { "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } },
3648 { "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } },
3649 { "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
3655 { "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }},
3656 { "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }},
3660 { "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
3662 { "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } },
3663 { "stux", X(31,183), X_MASK, PWRCOM, { RS, RA0, RB } },
3670 { "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } },
3692 { "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA0, RB } },
3694 { "stbx", X(31,215), X_MASK, COM, { RS, RA0, RB } },
3696 { "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } },
3697 { "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } },
3699 { "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } },
3700 { "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } },
3702 { "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA0, RB } },
3704 { "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }},
3715 { "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3716 { "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3717 { "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3718 { "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3729 { "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3730 { "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3731 { "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3732 { "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3733 { "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3734 { "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3735 { "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3736 { "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3738 { "icblce", X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }},
3739 { "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
3740 { "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },
3742 { "dcbtst", X(31,246), X_MASK, PPC, { CT, RA, RB } },
3744 { "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } },
3749 { "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } },
3751 { "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } },
3755 { "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
3756 { "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } },
3757 { "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } },
3758 { "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } },
3760 { "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3761 { "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3762 { "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3763 { "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3764 { "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3765 { "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3766 { "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3767 { "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3769 { "tlbiel", X(31,274), XRTLRA_MASK, POWER4, { RB, L } },
3773 { "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
3774 { "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
3776 { "dcbt", X(31,278), X_MASK, PPC, { CT, RA, RB } },
3778 { "lhzx", X(31,279), X_MASK, COM, { RT, RA0, RB } },
3780 { "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
3781 { "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
3783 { "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } },
3785 { "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA0, RB } },
3787 { "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L } },
3788 { "tlbi", X(31,306), XRT_MASK, POWER, { RA0, RB } },
3790 { "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
3792 { "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } },
3794 { "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
3795 { "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } },
3797 { "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } },
3835 { "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } },
3836 { "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } },
3837 { "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } },
3838 { "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } },
4031 { "lwax", X(31,341), X_MASK, PPC64, { RT, RA0, RB } },
4033 { "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
4034 { "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
4036 { "lhax", X(31,343), X_MASK, COM, { RT, RA0, RB } },
4038 { "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA0, RB } },
4040 { "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
4041 { "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
4043 { "dccci", X(31,454), XRT_MASK, PPC403|PPC440, { RA, RB } },
4050 { "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } },
4051 { "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } },
4052 { "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } },
4053 { "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } },
4057 { "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
4059 { "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
4061 { "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } },
4065 { "dcblc", X(31,390), X_MASK, PPCCHLK, { CT, RA, RB }},
4067 { "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
4068 { "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
4070 { "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
4071 { "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
4073 { "dcblce", X(31,398), X_MASK, PPCCHLK64, { CT, RA, RB }},
4075 { "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } },
4077 { "sthx", X(31,407), X_MASK, COM, { RS, RA0, RB } },
4079 { "cmpb", X(31,508), X_MASK, POWER6, { RA, RS, RB } },
4081 { "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
4083 { "lfdpx", X(31,791), X_MASK, POWER6, { FRT, RA, RB } },
4085 { "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
4087 { "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
4089 { "stfdpx", X(31,919), X_MASK, POWER6, { FRS, RA, RB } },
4091 { "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
4093 { "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
4094 { "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } },
4099 { "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA0, RB } },
4101 { "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } },
4103 { "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
4105 { "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } },
4107 { "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } },
4117 { "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
4119 { "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
4160 { "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
4161 { "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } },
4162 { "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } },
4163 { "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } },
4168 { "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
4169 { "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
4170 { "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
4171 { "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
4327 { "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
4329 { "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } },
4330 { "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } },
4332 { "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } },
4334 { "dcread", X(31,486), X_MASK, PPC403|PPC440, { RT, RA, RB }},
4338 { "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }},
4347 { "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } },
4348 { "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } },
4349 { "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } },
4350 { "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } },
4355 { "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
4356 { "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
4357 { "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
4358 { "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
4360 { "icbtlse", X(31,494), X_MASK, PPCCHLK64, { CT, RA, RB }},
4366 { "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } },
4375 { "ldbrx", X(31,532), X_MASK, CELL, { RT, RA0, RB } },
4377 { "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA0, RB } },
4378 { "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } },
4380 { "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA0, RB } },
4381 { "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } },
4383 { "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } },
4385 { "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } },
4386 { "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } },
4387 { "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } },
4388 { "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } },
4390 { "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } },
4391 { "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } },
4393 { "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } },
4394 { "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } },
4396 { "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } },
4397 { "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } },
4399 { "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA0, RB } },
4401 { "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA0, RB } },
4407 { "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } },
4409 { "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } },
4422 { "lfdx", X(31,599), X_MASK, COM, { FRT, RA0, RB } },
4424 { "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA0, RB } },
4426 { "mffgpr", XRC(31,607,0), XRA_MASK, POWER6, { FRT, RB } },
4428 { "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } },
4432 { "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } },
4434 { "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } },
4436 { "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } },
4438 { "stdbrx", X(31,660), X_MASK, CELL, { RS, RA0, RB } },
4440 { "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA0, RB } },
4441 { "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA0, RB } },
4443 { "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA0, RB } },
4444 { "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA0, RB } },
4446 { "stfsx", X(31,663), X_MASK, COM, { FRS, RA0, RB } },
4448 { "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } },
4449 { "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } },
4451 { "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } },
4452 { "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } },
4454 { "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA0, RB } },
4456 { "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA0, RB } },
4458 { "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } },
4463 { "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } },
4468 { "stfdx", X(31,727), X_MASK, COM, { FRS, RA0, RB } },
4470 { "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } },
4471 { "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } },
4473 { "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } },
4474 { "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
4476 { "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA0, RB } },
4480 { "dcba", X(31,758), XRT_MASK, PPC405 | BOOKE, { RA, RB } },
4482 { "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
4487 { "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB } },
4489 { "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } },
4491 { "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } },
4492 { "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } },
4494 { "lwzcix", X(31,789), X_MASK, POWER6, { RT, RA0, RB } },
4496 { "lhbrx", X(31,790), X_MASK, COM, { RT, RA0, RB } },
4498 { "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
4499 { "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } },
4500 { "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } },
4501 { "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } },
4503 { "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } },
4504 { "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } },
4506 { "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA0, RB } },
4508 { "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA0, RB } },
4509 { "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA0, RB } },
4511 { "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
4513 { "lhzcix", X(31,821), X_MASK, POWER6, { RT, RA0, RB } },
4523 { "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } },
4525 { "lbzcix", X(31,853), X_MASK, POWER6, { RT, RA0, RB } },
4530 { "lfiwax", X(31,855), X_MASK, POWER6, { FRT, RA0, RB } },
4532 { "ldcix", X(31,885), X_MASK, POWER6, { RT, RA0, RB } },
4534 { "tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE, { RTO, RA, RB } },
4535 { "tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE, { RTO, RA, RB } },
4536 { "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RTO, RA, RB } },
4537 { "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RTO, RA, RB } },
4539 { "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
4541 { "stwcix", X(31,917), X_MASK, POWER6, { RS, RA0, RB } },
4543 { "sthbrx", X(31,918), X_MASK, COM, { RS, RA0, RB } },
4545 { "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },
4546 { "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } },
4548 { "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } },
4549 { "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } },
4556 { "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA0, RB } },
4558 { "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA0, RB } },
4564 { "sthcix", X(31,949), X_MASK, POWER6, { RS, RA0, RB } },
4572 { "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } },
4574 { "iccci", X(31,966), XRT_MASK, PPC403|PPC440, { RA, RB } },
4579 { "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
4581 { "stbcix", X(31,981), X_MASK, POWER6, { RS, RA0, RB } },
4583 { "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
4585 { "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA0, RB } },
4590 { "icread", X(31,998), XRT_MASK, PPC403|PPC440, { RA, RB } },
4592 { "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } },
4593 { "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA0, RB } },
4595 { "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } },
4597 { "stdcix", X(31,1013), X_MASK, POWER6, { RS, RA0, RB } },
4599 { "dcbzl", XOPL(31,1014,1), XRT_MASK,POWER4, { RA, RB } },
4600 { "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4601 { "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4603 { "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } },
4605 { "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } },
4606 { "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } },
4607 { "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } },
4608 { "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } },
4609 { "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } },
4610 { "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } },
4611 { "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } },
4612 { "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } },
4613 { "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } },
4614 { "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } },
4615 { "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
4616 { "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
4619 { "lvlx", X(31, 519), X_MASK, CELL, { VD, RA0, RB } },
4620 { "lvlxl", X(31, 775), X_MASK, CELL, { VD, RA0, RB } },
4621 { "lvrx", X(31, 551), X_MASK, CELL, { VD, RA0, RB } },
4622 { "lvrxl", X(31, 807), X_MASK, CELL, { VD, RA0, RB } },
4623 { "stvlx", X(31, 647), X_MASK, CELL, { VS, RA0, RB } },
4624 { "stvlxl", X(31, 903), X_MASK, CELL, { VS, RA0, RB } },
4625 { "stvrx", X(31, 679), X_MASK, CELL, { VS, RA0, RB } },
4626 { "stvrxl", X(31, 935), X_MASK, CELL, { VS, RA0, RB } },