Cross Reference: /external/skia/third_party/glu/libtess/sweep.c

Lines Matching refs:Dst
71  * - for each e, e->Dst has been processed, but not e->Org
72  * - each edge e satisfies VertLeq(e->Dst,event) && VertLeq(event,e->Org)
129   if( e1->Dst == event ) {
130     if( e2->Dst == event ) {
135 	return EdgeSign( e2->Dst, e1->Org, e2->Org ) <= 0;
137       return EdgeSign( e1->Dst, e2->Org, e1->Org ) >= 0;
139     return EdgeSign( e2->Dst, event, e2->Org ) <= 0;
141   if( e2->Dst == event ) {
142     return EdgeSign( e1->Dst, event, e1->Org ) >= 0;
146   t1 = EdgeEval( e1->Dst, event, e1->Org );
147   t2 = EdgeEval( e2->Dst, event, e2->Org );
205   GLUvertex *dst = reg->eUp->Dst;
210   } while( reg->eUp->Dst == dst );
362     assert( VertLeq( e->Org, e->Dst ));
532     if( EdgeSign( eLo->Dst, eUp->Org, eLo->Org ) > 0 ) return FALSE;
547     if( EdgeSign( eUp->Dst, eLo->Org, eUp->Org ) < 0 ) return FALSE;
560  * eUp->Dst is above eLo, or eLo->Dst is below eUp (depending on which
565  * suppose at one point we checked eUp and eLo, and decided that eUp->Dst
568  * the test so that now eUp->Dst is incident to eLo, or barely below it.
582   assert( ! VertEq( eUp->Dst, eLo->Dst ));
584   if( VertLeq( eUp->Dst, eLo->Dst )) {
585     if( EdgeSign( eUp->Dst, eLo->Dst, eUp->Org ) < 0 ) return FALSE;
587     /* eLo->Dst is above eUp, so splice eLo->Dst into eUp */
594     if( EdgeSign( eLo->Dst, eUp->Dst, eLo->Org ) > 0 ) return FALSE;
596     /* eUp->Dst is below eLo, so splice eUp->Dst into eLo */
623   GLUvertex *dstUp = eUp->Dst;
624   GLUvertex *dstLo = eLo->Dst;
792     if( eUp->Dst != eLo->Dst ) {
793       /* Check that the edge ordering is obeyed at the Dst vertices. */
814       if(    eUp->Dst != eLo->Dst
816           && (eUp->Dst == tess->event || eLo->Dst == tess->event) )
837     if( eUp->Org == eLo->Org && eUp->Dst == eLo->Dst ) {
889   if( eUp->Dst != eLo->Dst ) {
963   if( ! VertEq( e->Dst, vEvent )) {
976   /* vEvent coincides with e->Dst, which has already been processed.
985     /* Here e->Dst has only a single fixable edge going right.
995     /* e->Dst had no left-going edges -- indicate this to AddRightEdges() */
1034   if( EdgeSign( eUp->Dst, vEvent, eUp->Org ) == 0 ) {
1040    * e->Dst is the vertex that we will connect to vEvent.
1042   reg = VertLeq( eLo->Dst, eUp->Dst ) ? regUp : regLo;
1144   e->Dst->s = -SENTINEL_COORD;
1145   e->Dst->t = t;
1146   tess->event = e->Dst;		/* initialize it */
1213     if( VertEq( e->Org, e->Dst ) && e->Lnext->Lnext != e ) {