Lines Matching refs:opcode

502   uint32_t opcode   = GetOpcodeField(instr);
507 return opcode == BEQ ||
508 opcode == BNE ||
509 opcode == BLEZ ||
510 opcode == BGTZ ||
511 opcode == BEQL ||
512 opcode == BNEL ||
513 opcode == BLEZL ||
514 opcode == BGTZL ||
515 (opcode == REGIMM && (rt_field == BLTZ || rt_field == BGEZ ||
517 (opcode == COP1 && rs_field == BC1) || // Coprocessor branch.
533 uint32_t opcode = GetOpcodeField(instr);
538 return opcode == J || opcode == JAL ||
539 (opcode == SPECIAL && rt_field == 0 &&
545 uint32_t opcode = GetOpcodeField(instr);
547 return opcode == J;
565 uint32_t opcode = GetOpcodeField(instr);
567 return opcode == LUI;
572 uint32_t opcode = GetOpcodeField(instr);
574 return opcode == ORI;
581 uint32_t opcode = GetOpcodeField(instr);
590 bool ret = (opcode == SLL &&
853 void Assembler::GenInstrRegister(Opcode opcode,
860 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift)
866 void Assembler::GenInstrRegister(Opcode opcode,
873 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift)
879 void Assembler::GenInstrRegister(Opcode opcode,
887 Instr instr = opcode | fmt | (ft.code() << kFtShift) | (fs.code() << kFsShift)
893 void Assembler::GenInstrRegister(Opcode opcode,
901 Instr instr = opcode | fmt | (rt.code() << kRtShift)
907 void Assembler::GenInstrRegister(Opcode opcode,
915 opcode | fmt | (rt.code() << kRtShift) | (fs.code() << kFsShift) | func;
922 void Assembler::GenInstrImmediate(Opcode opcode,
927 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift)
933 void Assembler::GenInstrImmediate(Opcode opcode,
938 Instr instr = opcode | (rs.code() << kRsShift) | SF | (j & kImm16Mask);
943 void Assembler::GenInstrImmediate(Opcode opcode,
949 Instr instr = opcode | (rs.code() << kRsShift) | (ft.code() << kFtShift)
955 void Assembler::GenInstrJump(Opcode opcode,
959 Instr instr = opcode | address;