Lines Matching refs:rs
543 void MacroAssembler::Addu(Register rd, Register rs, const Operand& rt) {
545 addu(rd, rs, rt.rm());
548 addiu(rd, rs, rt.imm32_);
551 ASSERT(!rs.is(at));
553 addu(rd, rs, at);
559 void MacroAssembler::Subu(Register rd, Register rs, const Operand& rt) {
561 subu(rd, rs, rt.rm());
564 addiu(rd, rs, -rt.imm32_); // No subiu instr, use addiu(x, y, -imm).
567 ASSERT(!rs.is(at));
569 subu(rd, rs, at);
575 void MacroAssembler::Mul(Register rd, Register rs, const Operand& rt) {
578 mult(rs, rt.rm());
581 mul(rd, rs, rt.rm());
585 ASSERT(!rs.is(at));
588 mult(rs, at);
591 mul(rd, rs, at);
597 void MacroAssembler::Mult(Register rs, const Operand& rt) {
599 mult(rs, rt.rm());
602 ASSERT(!rs.is(at));
604 mult(rs, at);
609 void MacroAssembler::Multu(Register rs, const Operand& rt) {
611 multu(rs, rt.rm());
614 ASSERT(!rs.is(at));
616 multu(rs, at);
621 void MacroAssembler::Div(Register rs, const Operand& rt) {
623 div(rs, rt.rm());
626 ASSERT(!rs.is(at));
628 div(rs, at);
633 void MacroAssembler::Divu(Register rs, const Operand& rt) {
635 divu(rs, rt.rm());
638 ASSERT(!rs.is(at));
640 divu(rs, at);
645 void MacroAssembler::And(Register rd, Register rs, const Operand& rt) {
647 and_(rd, rs, rt.rm());
650 andi(rd, rs, rt.imm32_);
653 ASSERT(!rs.is(at));
655 and_(rd, rs, at);
661 void MacroAssembler::Or(Register rd, Register rs, const Operand& rt) {
663 or_(rd, rs, rt.rm());
666 ori(rd, rs, rt.imm32_);
669 ASSERT(!rs.is(at));
671 or_(rd, rs, at);
677 void MacroAssembler::Xor(Register rd, Register rs, const Operand& rt) {
679 xor_(rd, rs, rt.rm());
682 xori(rd, rs, rt.imm32_);
685 ASSERT(!rs.is(at));
687 xor_(rd, rs, at);
693 void MacroAssembler::Nor(Register rd, Register rs, const Operand& rt) {
695 nor(rd, rs, rt.rm());
698 ASSERT(!rs.is(at));
700 nor(rd, rs, at);
705 void MacroAssembler::Neg(Register rs, const Operand& rt) {
707 ASSERT(!at.is(rs));
710 xor_(rs, rt.rm(), at);
714 void MacroAssembler::Slt(Register rd, Register rs, const Operand& rt) {
716 slt(rd, rs, rt.rm());
719 slti(rd, rs, rt.imm32_);
722 ASSERT(!rs.is(at));
724 slt(rd, rs, at);
730 void MacroAssembler::Sltu(Register rd, Register rs, const Operand& rt) {
732 sltu(rd, rs, rt.rm());
735 sltiu(rd, rs, rt.imm32_);
738 ASSERT(!rs.is(at));
740 sltu(rd, rs, at);
746 void MacroAssembler::Ror(Register rd, Register rs, const Operand& rt) {
749 rotrv(rd, rs, rt.rm());
751 rotr(rd, rs, rt.imm32_);
756 sllv(at, rs, at);
757 srlv(rd, rs, rt.rm());
761 srl(rd, rs, 0);
763 srl(at, rs, rt.imm32_);
764 sll(rd, rs, (0x20 - rt.imm32_) & 0x1f);
928 Register rs,
935 ext_(rt, rs, pos, size);
937 // Move rs to rt and shift it left then right to get the
940 sll(rt, rs, shift_left); // Acts as a move if shift_left == 0.
951 Register rs,
959 ins_(rt, rs, pos, size);
961 ASSERT(!rt.is(t8) && !rs.is(t8));
964 and_(t8, rs, at);
984 Register rs,
986 // Convert rs to a FP value in fd (and fd + 1).
987 // We do this by converting rs minus the MSB to avoid sign conversion,
991 ASSERT(!rs.is(t9));
992 ASSERT(!rs.is(at));
994 // Save rs's MSB to t9.
995 Ext(t9, rs, 31, 1);
996 // Remove rs's MSB.
997 Ext(at, rs, 0, 31);
1006 // If rs's MSB was 0, it's done.
1072 Register rs,
1075 ASSERT(!rs.is(at));
1086 // First we subtract 2^31 from fd, then trunc it to rs
1087 // and add 2^31 to rs.
1090 mfc1(rs, scratch);
1091 Or(rs, rs, 1 << 31);
1098 mfc1(rs, scratch);
1200 void MacroAssembler::Movz(Register rd, Register rs, Register rt) {
1204 mov(rd, rs);
1207 movz(rd, rs, rt);
1212 void MacroAssembler::Movn(Register rd, Register rs, Register rt) {
1216 mov(rd, rs);
1219 movn(rd, rs, rt);
1224 void MacroAssembler::Movt(Register rd, Register rs, uint16_t cc) {
1226 // Tests an FP condition code and then conditionally move rs to rd.
1229 ASSERT(!(rs.is(t8) || rd.is(t8)));
1242 mov(rd, rs);
1245 movt(rd, rs, cc);
1250 void MacroAssembler::Movf(Register rd, Register rs, uint16_t cc) {
1252 // Tests an FP condition code and then conditionally move rs to rd.
1255 ASSERT(!(rs.is(t8) || rd.is(t8)));
1268 mov(rd, rs);
1271 movf(rd, rs, cc);
1276 void MacroAssembler::Clz(Register rd, Register rs) {
1278 ASSERT(!(rd.is(t8) || rd.is(t9)) && !(rs.is(t8) || rs.is(t9)));
1282 mov(at, rs);
1293 clz(rd, rs);
1588 #define BRANCH_ARGS_CHECK(cond, rs, rt) ASSERT( \
1589 (cond == cc_always && rs.is(zero_reg) && rt.rm().is(zero_reg)) || \
1590 (cond != cc_always && (!rs.is(zero_reg) || !rt.rm().is(zero_reg))))
1598 void MacroAssembler::Branch(int16_t offset, Condition cond, Register rs,
1601 BranchShort(offset, cond, rs, rt, bdslot);
1622 void MacroAssembler::Branch(Label* L, Condition cond, Register rs,
1627 BranchShort(L, cond, rs, rt, bdslot);
1631 BranchShort(&skip, neg_cond, rs, rt);
1639 BranchShort(&skip, neg_cond, rs, rt);
1643 BranchShort(L, cond, rs, rt, bdslot);
1651 Register rs,
1655 Branch(L, cond, rs, Operand(at), bdslot);
1668 void MacroAssembler::BranchShort(int16_t offset, Condition cond, Register rs,
1671 BRANCH_ARGS_CHECK(cond, rs, rt);
1672 ASSERT(!rs.is(zero_reg));
1677 // NOTE: 'at' can be clobbered by Branch but it is legal to use it as rs or
1685 beq(rs, r2, offset);
1688 bne(rs, r2, offset);
1693 bgtz(rs, offset);
1695 slt(scratch, r2, rs);
1701 bgez(rs, offset);
1703 slt(scratch, rs, r2);
1709 bltz(rs, offset);
1711 slt(scratch, rs, r2);
1717 blez(rs, offset);
1719 slt(scratch, r2, rs);
1726 bgtz(rs, offset);
1728 sltu(scratch, r2, rs);
1734 bgez(rs, offset);
1736 sltu(scratch, rs, r2);
1745 sltu(scratch, rs, r2);
1753 sltu(scratch, r2, rs);
1770 ASSERT(!scratch.is(rs));
1773 beq(rs, r2, offset);
1777 ASSERT(!scratch.is(rs));
1780 bne(rs, r2, offset);
1785 bgtz(rs, offset);
1789 slt(scratch, r2, rs);
1795 bgez(rs, offset);
1797 slti(scratch, rs, rt.imm32_);
1802 slt(scratch, rs, r2);
1808 bltz(rs, offset);
1810 slti(scratch, rs, rt.imm32_);
1815 slt(scratch, rs, r2);
1821 blez(rs, offset);
1825 slt(scratch, r2, rs);
1832 bgtz(rs, offset);
1836 sltu(scratch, r2, rs);
1842 bgez(rs, offset);
1844 sltiu(scratch, rs, rt.imm32_);
1849 sltu(scratch, rs, r2);
1858 sltiu(scratch, rs, rt.imm32_);
1863 sltu(scratch, rs, r2);
1873 sltu(scratch, r2, rs);
1899 void MacroAssembler::BranchShort(Label* L, Condition cond, Register rs,
1902 BRANCH_ARGS_CHECK(cond, rs, rt);
1919 beq(rs, r2, offset);
1923 bne(rs, r2, offset);
1929 bgtz(rs, offset);
1931 slt(scratch, r2, rs);
1939 bgez(rs, offset);
1941 slt(scratch, rs, r2);
1949 bltz(rs, offset);
1951 slt(scratch, rs, r2);
1959 blez(rs, offset);
1961 slt(scratch, r2, rs);
1970 bgtz(rs, offset);
1972 sltu(scratch, r2, rs);
1980 bgez(rs, offset);
1982 sltu(scratch, rs, r2);
1992 sltu(scratch, rs, r2);
2002 sltu(scratch, r2, rs);
2020 ASSERT(!scratch.is(rs));
2024 beq(rs, r2, offset);
2027 ASSERT(!scratch.is(rs));
2031 bne(rs, r2, offset);
2037 bgtz(rs, offset);
2039 ASSERT(!scratch.is(rs));
2042 slt(scratch, r2, rs);
2050 bgez(rs, offset);
2052 slti(scratch, rs, rt.imm32_);
2056 ASSERT(!scratch.is(rs));
2059 slt(scratch, rs, r2);
2067 bltz(rs, offset);
2069 slti(scratch, rs, rt.imm32_);
2073 ASSERT(!scratch.is(rs));
2076 slt(scratch, rs, r2);
2084 blez(rs, offset);
2086 ASSERT(!scratch.is(rs));
2089 slt(scratch, r2, rs);
2098 bgtz(rs, offset);
2100 ASSERT(!scratch.is(rs));
2103 sltu(scratch, r2, rs);
2111 bgez(rs, offset);
2113 sltiu(scratch, rs, rt.imm32_);
2117 ASSERT(!scratch.is(rs));
2120 sltu(scratch, rs, r2);
2130 sltiu(scratch, rs, rt.imm32_);
2134 ASSERT(!scratch.is(rs));
2137 sltu(scratch, rs, r2);
2147 ASSERT(!scratch.is(rs));
2150 sltu(scratch, r2, rs);
2172 void MacroAssembler::BranchAndLink(int16_t offset, Condition cond, Register rs,
2175 BranchAndLinkShort(offset, cond, rs, rt, bdslot);
2196 void MacroAssembler::BranchAndLink(Label* L, Condition cond, Register rs,
2201 BranchAndLinkShort(L, cond, rs, rt, bdslot);
2205 BranchShort(&skip, neg_cond, rs, rt);
2213 BranchShort(&skip, neg_cond, rs, rt);
2217 BranchAndLinkShort(L, cond, rs, rt, bdslot);
2237 Register rs, const Operand& rt,
2239 BRANCH_ARGS_CHECK(cond, rs, rt);
2255 bne(rs, r2, 2);
2260 beq(rs, r2, 2);
2267 slt(scratch, r2, rs);
2272 slt(scratch, rs, r2);
2277 slt(scratch, rs, r2);
2282 slt(scratch, r2, rs);
2289 sltu(scratch, r2, rs);
2294 sltu(scratch, rs, r2);
2299 sltu(scratch, rs, r2);
2304 sltu(scratch, r2, rs);
2327 void MacroAssembler::BranchAndLinkShort(Label* L, Condition cond, Register rs,
2330 BRANCH_ARGS_CHECK(cond, rs, rt);
2348 bne(rs, r2, 2);
2354 beq(rs, r2, 2);
2362 slt(scratch, r2, rs);
2368 slt(scratch, rs, r2);
2374 slt(scratch, rs, r2);
2380 slt(scratch, r2, rs);
2388 sltu(scratch, r2, rs);
2394 sltu(scratch, rs, r2);
2400 sltu(scratch, rs, r2);
2406 sltu(scratch, r2, rs);
2427 Register rs,
2434 BRANCH_ARGS_CHECK(cond, rs, rt);
2435 Branch(2, NegateCondition(cond), rs, rt);
2447 Register rs,
2452 Branch(USE_DELAY_SLOT, &skip, NegateCondition(cond), rs, rt);
2465 Register rs,
2469 Jump(reinterpret_cast<intptr_t>(target), rmode, cond, rs, rt, bd);
2476 Register rs,
2480 Jump(reinterpret_cast<intptr_t>(code.location()), rmode, cond, rs, rt, bd);
2486 Register rs,
2507 Register rs,
2516 BRANCH_ARGS_CHECK(cond, rs, rt);
2517 Branch(2, NegateCondition(cond), rs, rt);
2524 ASSERT_EQ(CallSize(target, cond, rs, rt, bd),
2532 Register rs,
2535 int size = CallSize(t9, cond, rs, rt, bd);
2543 Register rs,
2554 Call(t9, cond, rs, rt, bd);
2555 ASSERT_EQ(CallSize(target, rmode, cond, rs, rt, bd),
2564 Register rs,
2568 rmode, cond, rs, rt, bd);
2576 Register rs,
2587 Call(reinterpret_cast<Address>(code.location()), rmode, cond, rs, rt, bd);
2588 ASSERT_EQ(CallSize(code, rmode, ast_id, cond, rs, rt, bd),
2594 Register rs,
2597 Jump(ra, cond, rs, rt, bd);
4327 Register rs, Operand rt) {
4329 Check(cc, msg, rs, rt);
4362 Register rs, Operand rt) {
4364 Branch(&L, cc, rs, rt);