Cross Reference: /external/valgrind/main/VEX/priv/guest_arm

Lines Matching defs:dD
10498       UInt dD      = (INSN(22,22) << 4) | INSN(15,12);
10523       if (dD + nRegs - 1 >= 32)
10570             putDReg(dD + i, loadLE(Ity_F64, addr), IRTemp_INVALID);
10572             storeLE(addr, getDReg(dD + i));
10589                       nm, nCC(conq), rN, dD, dD + nRegs - 1);
10592                       nm, nCC(conq), rN, dD, dD + nRegs - 1);
10595                       nm, nCC(conq), rN, dD, dD + nRegs - 1);
10635       UInt dD      = (INSN(22,22) << 4) | INSN(15,12);
10660       if (dD + nRegs - 1 >= 32)
10707             putDReg(dD + i, loadLE(Ity_F64, addr), IRTemp_INVALID);
10709             storeLE(addr, getDReg(dD + i));
10726                       nm, nCC(conq), rN, dD, dD + nRegs - 1);
10729                       nm, nCC(conq), rN, dD, dD + nRegs - 1);
10732                       nm, nCC(conq), rN, dD, dD + nRegs - 1);
10996    // VMOV.F64 dD, #imm
10997    // FCONSTD dD, #imm
11013    // VDUP dD, rT
11069       UInt dD     = INSN(15,12) | (INSN(22,22) << 4);
11088          putDReg(dD, loadLE(Ity_F64,mkexpr(ea)), IRTemp_INVALID);
11090          storeLE(mkexpr(ea), getDReg(dD));
11093           bL ? "ld" : "st", nCC(conq), dD, rN,
11103       UInt    dD  = INSN(15,12) | (INSN(22,22) << 4);   /* dst/acc */
11113             putDReg(dD, triop(Iop_AddF64, rm,
11114                               getDReg(dD),
11118             DIP("fmacd%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM);
11121             putDReg(dD, triop(Iop_AddF64, rm,
11122                               getDReg(dD),
11127             DIP("fnmacd%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM);
11130             putDReg(dD, triop(Iop_AddF64, rm,
11131                               unop(Iop_NegF64, getDReg(dD)),
11135             DIP("fmscd%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM);
11138             putDReg(dD, triop(Iop_AddF64, rm,
11139                               unop(Iop_NegF64, getDReg(dD)),
11144             DIP("fnmscd%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM);
11147             putDReg(dD, triop(Iop_MulF64, rm, getDReg(dN), getDReg(dM)),
11149             DIP("fmuld%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM);
11152             putDReg(dD, unop(Iop_NegF64,
11156             DIP("fnmuld%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM);
11159             putDReg(dD, triop(Iop_AddF64, rm, getDReg(dN), getDReg(dM)),
11161             DIP("faddd%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM);
11164             putDReg(dD, triop(Iop_SubF64, rm, getDReg(dN), getDReg(dM)),
11166             DIP("fsubd%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM);
11169             putDReg(dD, triop(Iop_DivF64, rm, getDReg(dN), getDReg(dM)),
11171             DIP("fdivd%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM);
11200       UInt dD = INSN(15,12) | (INSN(22,22) << 4);
11208          assign(argL, getDReg(dD));
11241             DIP("fcmpz%sd%s d%u\n", bN ? "e" : "", nCC(conq), dD);
11243             DIP("fcmp%sd%s d%u, d%u\n", bN ? "e" : "", nCC(conq), dD, dM);
11255       UInt dD  = INSN(15,12) | (INSN(22,22) << 4);
11261          putDReg(dD, getDReg(dM), condT);
11262          DIP("fcpyd%s d%u, d%u\n", nCC(conq), dD, dM);
11267          putDReg(dD, unop(Iop_AbsF64, getDReg(dM)), condT);
11268          DIP("fabsd%s d%u, d%u\n", nCC(conq), dD, dM);
11273          putDReg(dD, unop(Iop_NegF64, getDReg(dM)), condT);
11274          DIP("fnegd%s d%u, d%u\n", nCC(conq), dD, dM);
11280          putDReg(dD, binop(Iop_SqrtF64, rm, getDReg(dM)), condT);
11281          DIP("fsqrtd%s d%u, d%u\n", nCC(conq), dD, dM);
11292    // F{S,U}ITOD dD, fM
11299       UInt dD    = INSN(15,12) | (INSN(22,22) << 4);
11303          putDReg(dD, unop(Iop_I32StoF64,
11306          DIP("fsitod%s d%u, s%u\n", nCC(conq), dD, fM);
11309          putDReg(dD, unop(Iop_I32UtoF64,
11312          DIP("fuitod%s d%u, s%u\n", nCC(conq), dD, fM);
11842       UInt dD = INSN(15,12) | (INSN(22,22) << 4);
11845       putDReg(dD, unop(Iop_F32toF64, getFReg(fM)), condT);
11846       DIP("fcvtds%s d%u, s%u\n", nCC(conq), dD, fM);