Lines Matching defs:am

238 static Bool sane_AMode ( AMD64AMode* am )
240 switch (am->tag) {
243 toBool( hregClass(am->Aam.IR.reg) == HRcInt64
244 && (hregIsVirtual(am->Aam.IR.reg)
245 || am->Aam.IR.reg == hregAMD64_RBP()) );
248 toBool( hregClass(am->Aam.IRRS.base) == HRcInt64
249 && hregIsVirtual(am->Aam.IRRS.base)
250 && hregClass(am->Aam.IRRS.index) == HRcInt64
251 && hregIsVirtual(am->Aam.IRRS.index) );
340 //.. static X86AMode* advance4 ( X86AMode* am )
342 //.. X86AMode* am4 = dopyX86AMode(am);
1735 AMD64AMode* am
1741 addInstr(env, AMD64Instr_LoadEX( 1, False, am, dst ));
1745 addInstr(env, AMD64Instr_Alu64R( Aalu_MOV, AMD64RMI_Mem(am), dst ));
1869 AMD64AMode* am = iselIntExpr_AMode_wrk(env, e);
1870 vassert(sane_AMode(am));
1871 return am;
1968 vassert(sane_AMode(rmi->Armi.Mem.am));
2010 AMD64AMode* am = iselIntExpr_AMode(env, e->Iex.Load.addr);
2011 return AMD64RMI_Mem(am);
2094 vassert(sane_AMode(rm->Arm.Mem.am));
2418 //.. X86AMode* am = X86AMode_IR(e->Iex.Get.offset, hregX86_EBP());
2419 //.. X86AMode* am4 = advance4(am);
2422 //.. addInstr(env, X86Instr_Alu32R( Xalu_MOV, X86RMI_Mem(am), tLo ));
2431 //.. X86AMode* am
2434 //.. X86AMode* am4 = advance4(am);
2437 //.. addInstr(env, X86Instr_Alu32R( Xalu_MOV, X86RMI_Mem(am), tLo ));
2819 AMD64AMode* am;
2822 am = iselIntExpr_AMode(env, e->Iex.Load.addr);
2823 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 4, res, am));
2841 AMD64AMode* am = AMD64AMode_IR( e->Iex.Get.offset,
2844 addInstr(env, AMD64Instr_SseLdSt( True/*load*/, 4, res, am ));
2967 AMD64AMode* am;
2970 am = iselIntExpr_AMode(env, e->Iex.Load.addr);
2971 addInstr(env, AMD64Instr_SseLdSt( True/*load*/, 8, res, am ));
2976 AMD64AMode* am = AMD64AMode_IR( e->Iex.Get.offset,
2979 addInstr(env, AMD64Instr_SseLdSt( True/*load*/, 8, res, am ));
2984 AMD64AMode* am
2989 addInstr(env, AMD64Instr_SseLdSt( True/*load*/, 8, res, am ));
3274 AMD64AMode* am = iselIntExpr_AMode(env, e->Iex.Load.addr);
3275 addInstr(env, AMD64Instr_SseLdSt( True/*load*/, 16, dst, am ));
3821 AMD64AMode* am = iselIntExpr_AMode(env, stmt->Ist.Store.addr);
3823 addInstr(env, AMD64Instr_Alu64M(Aalu_MOV,ri,am));
3827 AMD64AMode* am = iselIntExpr_AMode(env, stmt->Ist.Store.addr);
3831 r,am));
3835 AMD64AMode* am = iselIntExpr_AMode(env, stmt->Ist.Store.addr);
3837 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 8, r, am));
3841 AMD64AMode* am = iselIntExpr_AMode(env, stmt->Ist.Store.addr);
3843 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 4, r, am));
3847 AMD64AMode* am = iselIntExpr_AMode(env, stmt->Ist.Store.addr);
3849 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 16, r, am));
3882 AMD64AMode* am = AMD64AMode_IR(stmt->Ist.Put.offset,
3884 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 16, vec, am));
3889 AMD64AMode* am = AMD64AMode_IR(stmt->Ist.Put.offset, hregAMD64_RBP());
3891 addInstr(env, AMD64Instr_SseLdSt( False/*store*/, 4, f32, am ));
3896 AMD64AMode* am = AMD64AMode_IR( stmt->Ist.Put.offset,
3898 addInstr(env, AMD64Instr_SseLdSt( False/*store*/, 8, f64, am ));
3906 AMD64AMode* am
3914 addInstr(env, AMD64Instr_SseLdSt( False/*store*/, 8, val, am ));
3919 addInstr(env, AMD64Instr_Store( 1, r, am ));
3924 addInstr(env, AMD64Instr_Alu64M( Aalu_MOV, ri, am ));
3944 AMD64AMode* am = iselIntExpr_AMode(env, stmt->Ist.WrTmp.data);
3946 if (am->tag == Aam_IR && am->Aam.IR.imm == 0) {
3950 HReg src = am->Aam.IR.reg;
3953 addInstr(env, AMD64Instr_Lea64(am,dst));
4050 AMD64AMode* am = iselIntExpr_AMode(env, cas->addr);
4066 addInstr(env, AMD64Instr_ACAS(am, sz));
4078 AMD64AMode* am = iselIntExpr_AMode(env, cas->addr);
4105 addInstr(env, AMD64Instr_DACAS(am, sz));