Lines Matching defs:argR
1167 HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
1169 addInstr(env, AMD64Instr_MovxLQ(False, argR, argR));
1171 addInstr(env, mk_iMOVsd_RR(argR, hregAMD64_RSI()) );
1427 IRExpr* argR = e->Iex.Unop.arg->Iex.Binop.arg2;
1442 AMD64RMI* rmi = iselIntExpr_RMI(env, argR);
3005 HReg argR = iselDblExpr(env, e->Iex.Triop.arg3);
3009 addInstr(env, AMD64Instr_Sse64FLo(op, argR, dst));
3486 HReg argR = iselVecExpr(env, e->Iex.Binop.arg2);
3489 addInstr(env, AMD64Instr_Sse32Fx4(op, argR, dst));
3506 HReg argR = iselVecExpr(env, e->Iex.Binop.arg2);
3509 addInstr(env, AMD64Instr_Sse64Fx2(op, argR, dst));
3525 HReg argR = iselVecExpr(env, e->Iex.Binop.arg2);
3528 addInstr(env, AMD64Instr_Sse32FLo(op, argR, dst));
3544 HReg argR = iselVecExpr(env, e->Iex.Binop.arg2);
3547 addInstr(env, AMD64Instr_Sse64FLo(op, argR, dst));
3684 HReg argR = iselVecExpr(env, e->Iex.Binop.arg2);
3708 movupd %argR, 0(%rdx)
3712 addInstr(env, AMD64Instr_SseLdSt(False/*!isLoad*/, 16, argR,
3735 HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
3760 addInstr(env, mk_iMOVsd_RR(argR, hregAMD64_RDX()));