Cross Reference: /system/core/libpixelflinger/codeflinger/MIPSAssembler.cpp

Lines Matching defs:Rm
234 uint32_t ArmToMipsAssembler::reg_imm(int Rm, int type, uint32_t shift)
236     amode.reg = Rm;
242 uint32_t ArmToMipsAssembler::reg_rrx(int Rm)
248 uint32_t ArmToMipsAssembler::reg_reg(int Rm, int type, int Rs)
256 // LDR(B)/STR(B)/PLD (immediate and Rm can be negative, which indicate U=0)
277 uint32_t ArmToMipsAssembler::reg_scale_pre(int Rm, int type,
282     amode.reg = Rm;
289 uint32_t ArmToMipsAssembler::reg_scale_post(int Rm, int type, uint32_t shift)
295 // LDRH/LDRSB/LDRSH/STRH (immediate and Rm can be negative, which indicate U=0)
319 uint32_t ArmToMipsAssembler::reg_pre(int Rm, int W)
322     amode.reg = Rm;
326 uint32_t ArmToMipsAssembler::reg_post(int Rm)
614         int Rd, int Rm, int Rs, int Rn) {
618     mMips->MUL(R_at, Rm, Rs);
627         int Rd, int Rm, int Rs) {
629     mMips->MUL(Rd, Rm, Rs);
637         int RdLo, int RdHi, int Rm, int Rs) {
639     mMips->MULT(Rm, Rs);
650         int RdLo, int RdHi, int Rm, int Rs) {
651     LOG_FATAL_IF(RdLo==Rm || RdHi==Rm || RdLo==RdHi,
652                         "UMUAL(r%u,r%u,r%u,r%u)", RdLo,RdHi,Rm,Rs);
654     //             (RdHi<<16) | (RdLo<<12) | (Rs<<8) | 0x90 | Rm;
666         int RdLo, int RdHi, int Rm, int Rs) {
667     LOG_FATAL_IF(RdLo==Rm || RdHi==Rm || RdLo==RdHi,
668                         "SMULL(r%u,r%u,r%u,r%u)", RdLo,RdHi,Rm,Rs);
670     //             (RdHi<<16) | (RdLo<<12) | (Rs<<8) | 0x90 | Rm;
681         int RdLo, int RdHi, int Rm, int Rs) {
682     LOG_FATAL_IF(RdLo==Rm || RdHi==Rm || RdLo==RdHi,
683                         "SMUAL(r%u,r%u,r%u,r%u)", RdLo,RdHi,Rm,Rs);
685     //             (RdHi<<16) | (RdLo<<12) | (Rs<<8) | 0x90 | Rm;
1005 void ArmToMipsAssembler::SWP(int cc, int Rn, int Rd, int Rm) {
1006     // *mPC++ = (cc<<28) | (2<<23) | (Rn<<16) | (Rd << 12) | 0x90 | Rm;
1012 void ArmToMipsAssembler::SWPB(int cc, int Rn, int Rd, int Rm) {
1013     // *mPC++ = (cc<<28) | (2<<23) | (1<<22) | (Rn<<16) | (Rd << 12) | 0x90 | Rm;
1042 void ArmToMipsAssembler::CLZ(int cc, int Rd, int Rm)
1045     mMips->CLZ(Rd, Rm);
1048 void ArmToMipsAssembler::QADD(int cc,  int Rd, int Rm, int Rn)
1050     // *mPC++ = (cc<<28) | 0x1000050 | (Rn<<16) | (Rd<<12) | Rm;
1056 void ArmToMipsAssembler::QDADD(int cc,  int Rd, int Rm, int Rn)
1058     // *mPC++ = (cc<<28) | 0x1400050 | (Rn<<16) | (Rd<<12) | Rm;
1064 void ArmToMipsAssembler::QSUB(int cc,  int Rd, int Rm, int Rn)
1066     // *mPC++ = (cc<<28) | 0x1200050 | (Rn<<16) | (Rd<<12) | Rm;
1072 void ArmToMipsAssembler::QDSUB(int cc,  int Rd, int Rm, int Rn)
1074     // *mPC++ = (cc<<28) | 0x1600050 | (Rn<<16) | (Rd<<12) | Rm;
1082                 int Rd, int Rm, int Rs)
1088     // where x corresponds to Rm and y to Rs
1090     // select half-reg for Rm
1093         mMips->SRA(R_at, Rm, 16);
1097             mMips->SEH(R_at, Rm);
1099             mMips->SLL(R_at, Rm, 16);
1121                 int Rd, int Rm, int Rs)
1135     mMips->MULT(Rm, R_at);
1139 // 16 x 16 signed multiply, accumulate: Rd = Rm{16} * Rs{16} + Rn
1141                 int Rd, int Rm, int Rs, int Rn)
1147     // where x corresponds to Rm and y to Rs
1149     // select half-reg for Rm
1152         mMips->SRA(R_at, Rm, 16);
1156             mMips->SEH(R_at, Rm);
1158             mMips->SLL(R_at, Rm, 16);
1181                 int RdHi, int RdLo, int Rs, int Rm)
1183     // *mPC++ = (cc<<28) | 0x1400080 | (RdHi<<16) | (RdLo<<12) | (Rs<<8) | (xy<<4) | Rm;
1190                 int Rd, int Rm, int Rs, int Rn)
1192     // *mPC++ = (cc<<28) | 0x1200080 | (Rd<<16) | (Rn<<12) | (Rs<<8) | (y<<4) | Rm;
1199 void ArmToMipsAssembler::UXTB16(int cc, int Rd, int Rm, int rotate)
1203     //Rd[31:16] := ZeroExtend((Rm ROR (8 * sh))[23:16]),
1204     //Rd[15:0] := ZeroExtend((Rm ROR (8 * sh))[7:0]). sh 0-3.
1206     mMips->ROTR(Rm, Rm, rotate * 8);
1207     mMips->AND(Rd, Rm, 0x00FF00FF);