Cross Reference: /system/core/libpixelflinger/codeflinger/MIPSAssembler.cpp

Lines Matching defs:offset
298     // uint32_t offset = abs(immed8);
310     // uint32_t offset = abs(immed8);
768 void ArmToMipsAssembler::LDR(int cc, int Rd, int Rn, uint32_t offset)
772     if (offset > AMODE_UNSUPPORTED) offset = 0;
773     switch (offset) {
802 void ArmToMipsAssembler::LDRB(int cc, int Rd, int Rn, uint32_t offset)
806     if (offset > AMODE_UNSUPPORTED) offset = 0;
807     switch (offset) {
831 void ArmToMipsAssembler::STR(int cc, int Rd, int Rn, uint32_t offset)
835     if (offset > AMODE_UNSUPPORTED) offset = 0;
836     switch (offset) {
851                 // No writeback so store offset by value
867 void ArmToMipsAssembler::STRB(int cc, int Rd, int Rn, uint32_t offset)
871     if (offset > AMODE_UNSUPPORTED) offset = 0;
872     switch (offset) {
895 void ArmToMipsAssembler::LDRH(int cc, int Rd, int Rn, uint32_t offset)
899     if (offset > AMODE_UNSUPPORTED) offset = 0;
900     switch (offset) {
923 void ArmToMipsAssembler::LDRSB(int cc, int Rd, int Rn, uint32_t offset)
930 void ArmToMipsAssembler::LDRSH(int cc, int Rd, int Rn, uint32_t offset)
937 void ArmToMipsAssembler::STRH(int cc, int Rd, int Rn, uint32_t offset)
941     if (offset > AMODE_UNSUPPORTED) offset = 0;
942     switch (offset) {
1033 void ArmToMipsAssembler::PLD(int Rn, uint32_t offset) {
1034     LOG_ALWAYS_FATAL_IF(!((offset&(1<<24)) && !(offset&(1<<21))),
1036     // *mPC++ = 0xF550F000 | (Rn<<16) | offset;
1397         int32_t offset = int32_t(target_pc - (bt.pc+1));
1398         *bt.pc |= offset & 0x00FFFF;
1699 void MIPSAssembler::LW(int Rt, int Rbase, int16_t offset)
1701     *mPC++ = (lw_op<<OP_SHF) | (Rbase<<RS_SHF) | (Rt<<RT_SHF) | (offset & MSK_16);
1704 void MIPSAssembler::SW(int Rt, int Rbase, int16_t offset)
1706     *mPC++ = (sw_op<<OP_SHF) | (Rbase<<RS_SHF) | (Rt<<RT_SHF) | (offset & MSK_16);
1710 void MIPSAssembler::LB(int Rt, int Rbase, int16_t offset)
1712     *mPC++ = (lb_op<<OP_SHF) | (Rbase<<RS_SHF) | (Rt<<RT_SHF) | (offset & MSK_16);
1715 void MIPSAssembler::LBU(int Rt, int Rbase, int16_t offset)
1717     *mPC++ = (lbu_op<<OP_SHF) | (Rbase<<RS_SHF) | (Rt<<RT_SHF) | (offset & MSK_16);
1720 void MIPSAssembler::SB(int Rt, int Rbase, int16_t offset)
1722     *mPC++ = (sb_op<<OP_SHF) | (Rbase<<RS_SHF) | (Rt<<RT_SHF) | (offset & MSK_16);
1726 void MIPSAssembler::LH(int Rt, int Rbase, int16_t offset)
1728     *mPC++ = (lh_op<<OP_SHF) | (Rbase<<RS_SHF) | (Rt<<RT_SHF) | (offset & MSK_16);
1731 void MIPSAssembler::LHU(int Rt, int Rbase, int16_t offset)
1733     *mPC++ = (lhu_op<<OP_SHF) | (Rbase<<RS_SHF) | (Rt<<RT_SHF) | (offset & MSK_16);
1736 void MIPSAssembler::SH(int Rt, int Rbase, int16_t offset)
1738     *mPC++ = (sh_op<<OP_SHF) | (Rbase<<RS_SHF) | (Rt<<RT_SHF) | (offset & MSK_16);
1741 void MIPSAssembler::LUI(int Rt, int16_t offset)
1743     *mPC++ = (lui_op<<OP_SHF) | (Rt<<RT_SHF) | (offset & MSK_16);
1805     // encoded as BEQ zero, zero, offset
1807                         | (0<<RS_SHF) | 0;  // offset filled in later