Cross Reference: /system/core/libpixelflinger/codeflinger/MIPSAssembler.cpp

Lines Matching defs:value
229     // ALOGW("immediate value %08x at pc %08x\n", immediate, (int)pc());
230     amode.value = immediate;
238     amode.value = shift;
262     amode.value = immed12;
273     amode.value = immed12;
284     // amode.value = shift;
315     amode.value = immed8;
348 // would be overwritten by this instruction. If so, move the value to a
351 // instruction will _also_ use this value (a defect of the simple 1-pass, one-
353 // save the value before it is overwritten. This costs an extra MOVE instr.
383         if ((!_signed && amode.value > 0xffff)
384                 || (_signed && ((int)amode.value < -32768 || (int)amode.value > 32767) )) {
385             mMips->LUI(tmpReg, (amode.value >> 16));
386             if (amode.value & 0x0000ffff) {
387                 mMips->ORI(tmpReg, tmpReg, (amode.value & 0x0000ffff));
392             source = amode.value;
397             case LSL: mMips->SLL(tmpReg, amode.reg, amode.value); break;
398             case LSR: mMips->SRL(tmpReg, amode.reg, amode.value); break;
399             case ASR: mMips->SRA(tmpReg, amode.reg, amode.value); break;
401                           mMips->ROTR(tmpReg, amode.reg, amode.value);
403                           mMips->RORIsyn(tmpReg, amode.reg, amode.value);
498             if (amode.value > 0xffff) {
499                 mMips->LUI(Rd, (amode.value >> 16));
500                 if (amode.value & 0x0000ffff) {
501                     mMips->ORI(Rd, Rd, (amode.value & 0x0000ffff));
504                 mMips->ORI(Rd, 0, amode.value);
508             case LSL: mMips->SLL(Rd, amode.reg, amode.value); break;
509             case LSR: mMips->SRL(Rd, amode.reg, amode.value); break;
510             case ASR: mMips->SRA(Rd, amode.reg, amode.value); break;
512                           mMips->ROTR(Rd, amode.reg, amode.value);
514                           mMips->RORIsyn(Rd, amode.reg, amode.value);
530             if (amode.value > 0xffff) {
531                 mMips->LUI(Rd, (amode.value >> 16));
532                 if (amode.value & 0x0000ffff) {
533                     mMips->ORI(Rd, Rd, (amode.value & 0x0000ffff));
536                 mMips->ORI(Rd, 0, amode.value);
540             case LSL: mMips->SLL(Rd, amode.reg, amode.value); break;
541             case LSR: mMips->SRL(Rd, amode.reg, amode.value); break;
542             case ASR: mMips->SRA(Rd, amode.reg, amode.value); break;
544                           mMips->ROTR(Rd, amode.reg, amode.value);
546                           mMips->RORIsyn(Rd, amode.reg, amode.value);
775             amode.value = 0;
782             mMips->LW(Rd, Rn, amode.value);
784                 mMips->ADDIU(Rn, Rn, amode.value);
792             mMips->ADDIU(Rn, Rn, amode.value);
809             amode.value = 0;
813             mMips->LBU(Rd, Rn, amode.value);
815                 mMips->ADDIU(Rn, Rn, amode.value);
820             mMips->ADDIU(Rn, Rn, amode.value);
838             amode.value = 0;
848                 mMips->ADDIU(Rn, Rn, amode.value);
851                 // No writeback so store offset by value
852                 mMips->SW(Rd, Rn, amode.value);
857             mMips->ADDIU(Rn, Rn, amode.value);  // post index always writes back
874             amode.value = 0;
878             mMips->SB(Rd, Rn, amode.value);
880                 mMips->ADDIU(Rn, Rn, amode.value);
885             mMips->ADDIU(Rn, Rn, amode.value);
902             amode.value = 0;
905             mMips->LHU(Rd, Rn, amode.value);
909             mMips->ADDIU(Rn, Rn, amode.value);
944             amode.value = 0;
947             mMips->SH(Rd, Rn, amode.value);
951             mMips->ADDIU(Rn, Rn, amode.value);
1342     // mArmPC[iArm] holds the value of the Mips-PC for the first MIPS
1415     char value[PROPERTY_VALUE_MAX];
1416     value[0] = '\0';
1418     property_get("debug.pf.disasm", value, "0");
1420     if (atoi(value) != 0) {