Lines Matching refs:reg_imm
44 MOV(AL, 0, s.reg, reg_imm(s.reg, ROR, 8));
46 MOV(AL, 0, s.reg, reg_imm(s.reg, ROR, 8));
49 MOV(AL, 0, s.reg, reg_imm(s.reg, ROR, 16));
84 ORR(AL, 0, s.reg, s.reg, reg_imm(s0, LSL, 8));
86 ORR(AL, 0, s.reg, s.reg, reg_imm(s0, LSL, 16));
91 ORR(AL, 0, s1, s1, reg_imm(s0, LSL, 8));
93 ORR(AL, 0, s.reg, s1, reg_imm(s0, LSL, 16));
125 MOV(AL, 0, d.reg, reg_imm(s, LSR, l)); // component = packed >> l;
141 MOV(AL, 0, d.reg, reg_imm(s, LSL, 32-h));
149 MOV(AL, 0, d.reg, reg_imm(s, LSR, l)); // component = packed >> l;
217 RSB(AL, 0, d, s, reg_imm(s, LSL, dbits));
223 MOV(AL, 0, d, reg_imm(s, LSL, dbits-sbits));
227 ORR(AL, 0, d, d, reg_imm(d, LSR, sbits));
237 ORR(AL, 0, d, s, reg_imm(s, LSL, sbits));
315 MOV(AL, 0, ireg, reg_imm(s.reg, LSL, 32-sh));
344 MOV(AL, 0, ireg, reg_imm(s.reg, LSR, sl));
350 SUB(AL, 0, ireg, s.reg, reg_imm(s.reg, LSR, dbits));
352 if (shift>0) ADD(AL, 0, ireg, ireg, reg_imm(dither.reg, LSR, shift));
353 else if (shift<0) ADD(AL, 0, ireg, ireg, reg_imm(dither.reg, LSL,-shift));
361 MOV(AL, 0, ireg, reg_imm(s.reg, LSR, shift));
363 MOV(AL, 0, d.reg, reg_imm(ireg, LSL, dl));
365 ORR(AL, 0, d.reg, d.reg, reg_imm(ireg, LSL, dl));
369 MOV(AL, 0, d.reg, reg_imm(s.reg, LSR, shift));
371 ORR(AL, 0, d.reg, d.reg, reg_imm(s.reg, LSR, shift));
378 MOV(AL, 0, d.reg, reg_imm(s.reg, LSR, shift));
380 ORR(AL, 0, d.reg, d.reg, reg_imm(s.reg, LSR, shift));
384 MOV(AL, 0, d.reg, reg_imm(s.reg, LSL, -shift));
386 ORR(AL, 0, d.reg, d.reg, reg_imm(s.reg, LSL, -shift));