Searched defs:I64 (Results 1 - 3 of 3) sorted by relevance
| /external/valgrind/main/none/tests/amd64/ |
| H A D | rcl-amd64.c | 4 #define I64(C) "rcrq %%rbx\n" "rclq $" #C ",%%rax\n" "rclq %%rbx\n" macro
12 asm(I64(C) : "+a"(a), "+b"(b) : /* */); \
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| /external/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 1656 I64, enumerator in enum:AtomicSz
1768 Opc = AtomicOpcTbl[Op][I64];
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| /external/qemu/ |
| H A D | mips-dis.c | 922 The I64 format uses IMM8.
1117 #define I64 INSN_ISA64
1545 {"dclo", "U,s", 0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 },
1546 {"dclz", "U,s", 0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 },
1600 {"dmfc0", "t,+D", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 },
1601 {"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 },
1605 {"dmtc0", "t,+D", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 },
1606 {"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 },
2390 {"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I64 },
2392 {"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I64 },
1116 #define I64 macro
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