| /external/llvm/include/llvm/CodeGen/ |
| H A D | MachineScheduler.h | 46 const MachineDominatorTree *MDT; member in struct:llvm::MachineSchedContext
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| H A D | ScheduleDAGInstrs.h | 39 const MachineDominatorTree &MDT; member in class:llvm::LoopDependencies
46 LoopDependencies(const MachineDominatorTree &mdt) : MDT(mdt) {}
59 const MachineDomTreeNode *Node = MDT.getNode(Header);
177 const MachineDominatorTree &MDT; member in class:llvm::ScheduleDAGInstrs
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| /external/llvm/lib/CodeGen/ |
| H A D | UnreachableBlockElim.cpp | 128 MachineDominatorTree *MDT = getAnalysisIfAvailable<MachineDominatorTree>(); local
149 if (MDT && MDT->getNode(BB)) MDT->eraseNode(BB);
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| H A D | DFAPacketizer.cpp | 109 MachineDominatorTree &MDT, bool IsPostRA);
116 MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
118 ScheduleDAGInstrs(MF, MLI, MDT, IsPostRA) {
129 MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
133 VLIWScheduler = new DefaultVLIWScheduler(MF, MLI, MDT, IsPostRA);
115 DefaultVLIWScheduler( MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT, bool IsPostRA) argument
128 VLIWPacketizerList( MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT, bool IsPostRA) argument
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| H A D | LiveRangeCalc.cpp | 23 MachineDominatorTree *MDT,
27 DomTree = MDT;
21 reset(const MachineFunction *MF, SlotIndexes *SI, MachineDominatorTree *MDT, VNInfo::Allocator *VNIA) argument
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| H A D | SplitKit.h | 215 MachineDominatorTree &MDT; member in class:llvm::SplitEditor
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| H A D | PostRASchedulerList.cpp | 134 MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
197 MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
201 : ScheduleDAGInstrs(MF, MLI, MDT, /*IsPostRA=*/true), Topo(SUnits), AA(AA),
258 MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>(); local
291 SchedulePostRATDList Scheduler(Fn, MLI, MDT, AA, RegClassInfo, AntiDepMode,
196 SchedulePostRATDList( MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT, AliasAnalysis *AA, const RegisterClassInfo &RCI, TargetSubtargetInfo::AntiDepBreakMode AntiDepMode, SmallVectorImpl<const TargetRegisterClass*> &CriticalPathRCs) argument
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| H A D | InlineSpiller.cpp | 59 MachineDominatorTree &MDT; member in class:__anon8665::InlineSpiller
143 MDT(pass.getAnalysis<MachineDominatorTree>()),
440 MDT.dominates(SV.SpillMBB, DepSV.SpillMBB))) {
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| H A D | LiveDebugVariables.cpp | 224 /// @param MDT Dominator tree.
228 LiveIntervals &LIS, MachineDominatorTree &MDT,
247 LiveIntervals &LIS, MachineDominatorTree &MDT,
286 MachineDominatorTree *MDT; member in class:__anon8669::LDVImpl
488 LiveIntervals &LIS, MachineDominatorTree &MDT,
537 MDT.getNode(MBB)->getChildren();
623 MachineDominatorTree &MDT,
639 extendDef(Idx, LocNo, 0, 0, 0, LIS, MDT, UVS);
652 extendDef(Idx, LocNo, LI, VNI, &Kills, LIS, MDT, UVS);
663 extendDef(Idx, LocNo, LI, VNI, 0, LIS, MDT, UV
485 extendDef(SlotIndex Idx, unsigned LocNo, LiveInterval *LI, const VNInfo *VNI, SmallVectorImpl<SlotIndex> *Kills, LiveIntervals &LIS, MachineDominatorTree &MDT, UserValueScopes &UVS) argument
620 computeIntervals(MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, LiveIntervals &LIS, MachineDominatorTree &MDT, UserValueScopes &UVS) argument
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonVLIWPacketizer.cpp | 102 MachineDominatorTree &MDT);
158 MachineFunction &MF, MachineLoopInfo &MLI,MachineDominatorTree &MDT)
159 : VLIWPacketizerList(MF, MLI, MDT, true){
165 MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>(); local
168 HexagonPacketizerList Packetizer(Fn, MLI, MDT);
157 HexagonPacketizerList( MachineFunction &MF, MachineLoopInfo &MLI,MachineDominatorTree &MDT) argument
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