Searched defs:getReg (Results 1 - 18 of 18) sorted by relevance

/external/llvm/include/llvm/MC/
H A DMachineLocation.h52 unsigned getReg() const { return Register; } function in class:llvm::MachineLocation
H A DMCInst.h62 /// getReg - Returns the register number.
63 unsigned getReg() const { function in class:llvm::MCOperand
/external/dexmaker/src/dx/java/com/android/dx/rop/code/
H A DRegisterSpec.java326 public int getReg() { method in class:RegisterSpec
442 if ((other == null) || (reg != other.getReg())) {
/external/llvm/include/llvm/CodeGen/
H A DLiveRangeEdit.h119 unsigned getReg() const { return getParent().reg; } function in class:llvm::LiveRangeEdit
139 return createFrom(getReg());
H A DCallingConvLower.h67 static CCValAssign getReg(unsigned ValNo, MVT ValVT, function in class:llvm::CCValAssign
85 Ret = getReg(ValNo, ValVT, RegNo, LocVT, HTP);
H A DMachineOperand.h256 /// getReg - Returns the register number.
257 unsigned getReg() const { function in class:llvm::MachineOperand
H A DMachineFrameInfo.h44 unsigned getReg() const { return Reg; } function in class:llvm::CalleeSavedInfo
H A DScheduleDAG.h219 /// getReg - Return the register associated with this edge. This is
222 unsigned getReg() const { function in class:llvm::SDep
224 "getReg called on non-register dependence edge!");
H A DSelectionDAGNodes.h1459 unsigned getReg() const { return Reg; } function in class:llvm::SDNode::RegisterSDNode
/external/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp320 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { function
333 unsigned Reg = getReg(Decoder, Mips::CPU64RegsRegClassID, RegNo);
344 unsigned Reg = getReg(Decoder, Mips::CPURegsRegClassID, RegNo);
356 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
368 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
389 Reg = getReg(Decoder, Mips::CPURegsRegClassID, Reg);
390 Base = getReg(Decoder, Mips::CPURegsRegClassID, Base);
411 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
412 Base = getReg(Decoder, Mips::CPURegsRegClassID, Base);
450 unsigned Reg = getReg(Decode
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/external/llvm/lib/Target/Hexagon/
H A DHexagonHardwareLoops.cpp139 unsigned getReg() const { function in class:__anon8898::CountValue
158 if (isReg()) { OS << PrintReg(getReg()); }
281 unsigned DefReg = MPhi->getOperand(0).getReg();
287 const MachineInstr *DI = MRI->getVRegDef(MPhi->getOperand(i).getReg());
332 RI = MRI->reg_begin(IV_Opnd->getReg()), RE = MRI->reg_end();
341 const MachineInstr *IV_DefInstr = MRI->getVRegDef(IV_Opnd->getReg());
351 return new CountValue(InitialValue->getReg(), iv_value > 0);
354 const MachineInstr *DefInstr = MRI->getVRegDef(InitialValue->getReg());
376 Hexagon::ADD_ri && MI->getOperand(1).getReg() == IVReg);
396 (MO.getReg()
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/external/llvm/lib/Target/MBlaze/AsmParser/
H A DMBlazeAsmParser.cpp145 unsigned getReg() const { function in struct:__anon8910::MBlazeOperand
193 Inst.addOperand(MCOperand::CreateReg(getReg()));
290 OS << getMBlazeRegisterNumbering(getReg()) << ">";
379 Op = MBlazeOperand::CreateMem(Base.getReg(), Offset.getReg(), S, E);
381 Op = MBlazeOperand::CreateMem(Base.getReg(), Offset.getImm(), S, E);
/external/llvm/lib/Target/PowerPC/
H A DPPCCTRLoops.cpp152 unsigned getReg() const { function in class:__anon8964::CountValue
171 if (isReg()) { OS << PrintReg(getReg()); }
261 unsigned DefReg = MPhi->getOperand(0).getReg();
267 MachineInstr *DI = MRI->getVRegDef(MPhi->getOperand(i).getReg());
303 unsigned PredReg = LastI->getOperand(1).getReg();
341 RI = MRI->reg_begin(IV_Opnd->getReg()), RE = MRI->reg_end();
347 MI->getOperand(0).getReg() == PredReg) {
363 const MachineInstr *IV_DefInstr = MRI->getVRegDef(IV_Opnd->getReg());
369 unsigned InitialValueReg = InitialValue->getReg();
378 MRI->getVRegDef(DefInstr->getOperand(0).getReg());
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/external/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp102 unsigned getReg(int RC,int RegNo);
160 Inst.addOperand(MCOperand::CreateReg(getReg()));
198 unsigned getReg() const { function in class:__anon8937::MipsOperand
369 return getReg(Mips::FGR32RegClassID, IntVal);
372 return getReg(Mips::FGR64RegClassID, IntVal);
377 return getReg(Mips::AFGR64RegClassID, IntVal/2);
412 unsigned MipsAsmParser::getReg(int RC,int RegNo){ function in class:MipsAsmParser
428 return getReg(Mips::CPURegsRegClassID,RegNum);
703 int RegNo = op->getReg();
/external/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp220 unsigned getReg() const { function in struct:__anon8982::X86Operand
383 Inst.addOperand(MCOperand::CreateReg(getReg()));
1149 if (Op.isReg() && Op.getReg() == X86::DX && isDstOp(Op2)) {
1162 if (isSrcOp(Op) && Op2.isReg() && Op2.getReg() == X86::DX) {
1191 unsigned reg = Op2->getReg();
1221 unsigned reg = Op1->getReg();
/external/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp113 ExplicitSubRegs.push_back(RegBank.getReg(SRs[i]));
128 CodeGenRegister *Reg = RegBank.getReg(Aliases[i]);
159 const CodeGenRegister *getReg() const { assert(isValid()); return *RegI; } function in class:__anon9305::RegUnitIterator
716 const CodeGenRegister *Reg = RegBank.getReg((*Elements)[i]);
728 CodeGenRegister *Reg = RegBank.getReg(Order.back());
787 if (contains(RegBank.getReg(Super.Orders[i][j])))
973 getReg(Regs[i]);
981 getReg((*TupRegs)[j]);
1046 CodeGenRegister *CodeGenRegBank::getReg(Record *Def) { function in class:CodeGenRegBank
1278 if (Reg != UnitI.getReg()) {
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H A DDAGISelMatcher.h828 const CodeGenRegister *getReg() const { return Reg; } function in class:llvm::EmitRegisterMatcher
/external/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp508 unsigned getReg() const { function in class:__anon8852::ARMOperand
1440 Inst.addOperand(MCOperand::CreateReg(getReg()));
1445 Inst.addOperand(MCOperand::CreateReg(getReg()));
2333 OS << "<ccout " << getReg() << ">";
2385 OS << "<register " << getReg() << ">";
2545 int SrcReg = PrevOp->getReg();
4144 ((ARMOperand*)Operands[4])->getReg() ==
4145 ((ARMOperand*)Operands[3])->getReg())
4822 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4830 static_cast<ARMOperand*>(Operands[1])->getReg()
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