| /external/skia/src/svg/ |
| H A D | SkSVGDefs.cpp | 14 bool SkSVGDefs::isDef() { function in class:SkSVGDefs
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| H A D | SkSVGMetadata.cpp | 15 bool SkSVGMetadata::isDef() { function in class:SkSVGMetadata
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| H A D | SkSVGMask.cpp | 23 bool SkSVGMask::isDef() { function in class:SkSVGMask
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| H A D | SkSVGClipPath.cpp | 16 bool SkSVGClipPath::isDef() { function in class:SkSVGClipPath
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| H A D | SkSVGGroup.cpp | 26 bool SkSVGGroup::isDef() { function in class:SkSVGGroup
27 return fParent ? fParent->isDef() : false;
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| H A D | SkSVGElements.cpp | 44 bool SkSVGElement::isDef() { function in class:SkSVGElement
45 return isGroupParent() == false ? fParent->isDef() : fIsDef;
77 fIsDef = isDef();
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| H A D | SkSVGGradient.cpp | 21 bool SkSVGGradient::isDef() { function in class:SkSVGGradient
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| H A D | SkSVGParser.cpp | 232 void SkSVGParser::translate(SkSVGElement* element, bool isDef) { argument
236 (element->fIsDef && isDef == false && element->fIsNotDef == false) ||
237 (element->fIsDef == false && isDef && element->fIsNotDef)) {
252 element->fPaintState.flush(*this, isFlushable, isDef);
253 element->translate(*this, isDef);
256 if (element->fPaintState.flush(*this, isFlushable, isDef)) {
263 element->fPaintState.flush(*this, isFlushable, isDef);
265 element->translate(*this, isDef);
389 bool isDef = created->fIsDef = created->isDef(); local
[all...] |
| /external/llvm/include/llvm/Analysis/ |
| H A D | MemoryDependenceAnalysis.h | 130 /// isDef - Return true if this MemDepResult represents a query that is
132 bool isDef() const { return Value.getInt() == Def; } function in class:llvm::MemDepResult
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| /external/llvm/lib/CodeGen/ |
| H A D | MachineInstr.cpp | 130 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp, argument
148 IsDef = isDef;
178 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
217 return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
269 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
273 if (isDef()) {
866 if (MO.isDef()) {
1120 if (!MO.isReg() || !MO.isDef())
1173 assert(DefMO.isDef()
[all...] |
| H A D | LiveIntervalAnalysis.cpp | 172 if (MO.getReg() == Reg && MO.isDef()) {
433 if (MO.isDef())
845 LiveIntervals::getSpillWeight(bool isDef, bool isUse, unsigned loopDepth) { argument
859 return (isDef + isUse) * lc;
1131 if (MO.isDef()) {
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| /external/llvm/lib/Target/NVPTX/ |
| H A D | VectorElementize.cpp | 179 if (!oper.isDef()) continue;
510 std::vector<bool> isDef; local
516 isDef.push_back(oper.isDef());
518 isDef.push_back(false);
533 copy->addOperand(MachineOperand::CreateReg(scalarRegs[i], isDef[j]));
612 if (oper.isDef()) continue;
640 if (oper.isDef())
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| /external/llvm/include/llvm/CodeGen/ |
| H A D | MachineOperand.h | 272 bool isDef() const { function in class:llvm::MachineOperand
531 void ChangeToRegister(unsigned Reg, bool isDef, bool isImp = false,
557 static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false,
565 Op.IsDef = isDef;
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| /external/clang/lib/Sema/ |
| H A D | SemaStmtAsm.cpp | 594 bool isDef = NumDefs && (MCIdx < NumDefs); local
597 if (Op.isReg() && isDef) {
627 if (isDef || isMemDef) {
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMLoadStoreOptimizer.cpp | 345 bool isDef = (isi32Load(Opcode) || Opcode == ARM::VLDRS || local
353 MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef)
404 if (!MO->isReg() || !MO->isDef() || !MO->isImplicit() || MO->isDead())
520 if (MO.isDef() && MO.getReg() == ARM::CPSR && !MO.isDead())
1074 int Offset, bool isDef,
1081 if (isDef) {
1247 bool isKill = MO.isDef() ? false : MO.isKill();
1528 if (MO.isDef() && TRI->regsOverlap(Reg, Base))
1072 InsertLDR_STR(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, int Offset, bool isDef, DebugLoc dl, unsigned NewOpc, unsigned Reg, bool RegDeadKill, bool RegUndef, unsigned BaseReg, bool BaseKill, bool BaseUndef, bool OffKill, bool OffUndef, ARMCC::CondCodes Pred, unsigned PredReg, const TargetInstrInfo *TII, bool isT2) argument
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