/dalvik/libdex/ |
H A D | DexOpcodes.cpp | 295 const char* dexGetOpcodeName(Opcode op) argument 297 assert(op >= 0 && op < kNumPackedOpcodes); 298 return gOpNames[op];
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/dalvik/vm/compiler/codegen/arm/FP/ |
H A D | Thumb2VFP.cpp | 21 int op = kThumbBkpt; local 31 op = kThumb2Vadds; 35 op = kThumb2Vsubs; 39 op = kThumb2Vdivs; 43 op = kThumb2Vmuls; 57 newLIR3(cUnit, (ArmOpcode)op, rlResult.lowReg, rlSrc1.lowReg, 67 int op = kThumbBkpt; local 73 op = kThumb2Vaddd; 77 op = kThumb2Vsubd; 81 op 114 int op = kThumbBkpt; local [all...] |
/dalvik/vm/compiler/codegen/mips/FP/ |
H A D | MipsFP.cpp | 72 int op = kMipsNop; local 82 op = kMipsFadds; 86 op = kMipsFsubs; 90 op = kMipsFdivs; 94 op = kMipsFmuls; 107 newLIR3(cUnit, (MipsOpCode)op, rlResult.lowReg, rlSrc1.lowReg, rlSrc2.lowReg); 162 int op = kMipsNop; local 168 op = kMipsFaddd; 172 op = kMipsFsubd; 176 op 254 int op = kMipsNop; local [all...] |
/dalvik/vm/compiler/codegen/x86/libenc/ |
H A D | enc_base.cpp | 463 const Operand& op = opnds[idx]; local 464 assert(op.is_mem()); 476 RegName base = op.base(); 478 if (base == RegName_Null && op.index() == RegName_Null) { 479 assert(op.scale() == 0); // 'scale!=0' has no meaning without index 496 *(unsigned*)stream = (unsigned)op.disp(); 505 const bool disp_fits8 = CHAR_MIN <= op.disp() && op.disp() <= CHAR_MAX; 506 /*&& op.base() != RegName_Null - just checked above*/ 507 if (op [all...] |
/dalvik/dx/src/com/android/dx/cf/code/ |
H A D | RopperMachine.java | 109 * {@code null-ok;} the appropriate {@code return} op or {@code null} 321 * arrangement specified by the stack op pattern. 609 * The op athrow is the only one where it's possible 722 * @param op {@code non-null;} the opcode to use 725 private void updateReturnOp(Rop op, SourcePosition pos) { argument 726 if (op == null) { 727 throw new NullPointerException("op == null"); 735 returnOp = op; 738 if (returnOp != op) { 739 throw new SimException("return op mismatc [all...] |
/dalvik/vm/compiler/codegen/arm/Thumb/ |
H A D | Factory.cpp | 143 static ArmLIR *opNone(CompilationUnit *cUnit, OpKind op) argument 146 switch (op) { 162 static ArmLIR *opImm(CompilationUnit *cUnit, OpKind op, int value) argument 165 switch (op) { 179 static ArmLIR *opReg(CompilationUnit *cUnit, OpKind op, int rDestSrc) argument 182 switch (op) { 193 static ArmLIR *opRegImm(CompilationUnit *cUnit, OpKind op, int rDestSrc1, argument 201 switch (op) { 242 if (op == kOpCmp) 250 static ArmLIR *opRegRegReg(CompilationUnit *cUnit, OpKind op, in argument 278 opRegRegImm(CompilationUnit *cUnit, OpKind op, int rDest, int rSrc1, int value) argument 373 opRegReg(CompilationUnit *cUnit, OpKind op, int rDestSrc1, int rSrc2) argument [all...] |
/dalvik/vm/compiler/codegen/mips/Mips32/ |
H A D | Factory.cpp | 155 static MipsLIR *opNone(CompilationUnit *cUnit, OpKind op) argument 159 switch (op) { 186 static MipsLIR *opReg(CompilationUnit *cUnit, OpKind op, int rDestSrc) argument 189 switch (op) { 199 static MipsLIR *opRegRegImm(CompilationUnit *cUnit, OpKind op, int rDest, 201 static MipsLIR *opRegImm(CompilationUnit *cUnit, OpKind op, int rDestSrc1, argument 209 switch (op) { 211 return opRegRegImm(cUnit, op, rDestSrc1, rDestSrc1, value); 214 return opRegRegImm(cUnit, op, rDestSrc1, rDestSrc1, value); 226 if (op 234 opRegRegReg(CompilationUnit *cUnit, OpKind op, int rDest, int rSrc1, int rSrc2) argument 274 opRegRegImm(CompilationUnit *cUnit, OpKind op, int rDest, int rSrc1, int value) argument 365 opRegReg(CompilationUnit *cUnit, OpKind op, int rDestSrc1, int rSrc2) argument [all...] |
/dalvik/vm/compiler/codegen/x86/ |
H A D | Lower.cpp | 42 LowOp* op; variable
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H A D | LowerHelper.cpp | 226 LowOpImm* op = (LowOpImm*)atomNew(sizeof(LowOpImm)); local 227 op->lop.opCode = Mnemonic_NULL; 228 op->lop.opCode2 = cc; 229 op->lop.opnd1.type = LowOpndType_Imm; 230 op->lop.numOperands = 1; 231 op->immOpnd.value = imm; 233 return op; 395 LowOpRegReg* op = NULL; local 406 op = lower_reg_reg(m, m2, size, regAll, regAll2, type); 411 return op; 536 LowOpRegReg* op = (LowOpRegReg*)atomNew(sizeof(LowOpRegReg)); local 838 load_fp_stack(LowOp* op, OpndSize size, int disp, int base_reg, bool isBasePhysical) argument 858 store_fp_stack(LowOp* op, bool pop, OpndSize size, int disp, int base_reg, bool isBasePhysical) argument 865 store_int_fp_stack(LowOp* op, bool pop, OpndSize size, int disp, int base_reg, bool isBasePhysical) argument 872 compare_reg_mem(LowOp* op, OpndSize size, int reg, bool isPhysical, int disp, int base_reg, bool isBasePhysical) argument 1144 compare_ss_mem_reg(LowOp* op, int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical) argument 1153 compare_ss_reg_with_reg(LowOp* op, int reg1, bool isPhysical1, int reg2, bool isPhysical2) argument 1161 compare_sd_mem_with_reg(LowOp* op, int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical) argument 1170 compare_sd_reg_with_reg(LowOp* op, int reg1, bool isPhysical1, int reg2, bool isPhysical2) argument 1222 alu_unary_mem(LowOp* op, OpndSize size, ALU_Opcode opc, int disp, int base_reg, bool isBasePhysical) argument 1394 fpu_mem(LowOp* op, ALU_Opcode opc, OpndSize size, int disp, int base_reg, bool isBasePhysical) argument 1520 moves_mem_to_reg(LowOp* op, OpndSize size, int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical) argument 1624 set_VR_to_imm_noupdateref(LowOp* op, u2 vA, OpndSize size, int imm) argument 1669 move_ss_mem_to_reg(LowOp* op, int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical) argument 1677 move_ss_reg_to_mem(LowOp* op, int reg, bool isPhysical, int disp, int base_reg, bool isBasePhysical) argument 1691 move_sd_reg_to_mem(LowOp* op, int reg, bool isPhysical, int disp, int base_reg, bool isBasePhysical) argument [all...] |
/dalvik/vm/compiler/codegen/arm/Thumb2/ |
H A D | Factory.cpp | 234 static ArmLIR *opNone(CompilationUnit *cUnit, OpKind op) argument 237 switch (op) { 252 static ArmLIR *opImm(CompilationUnit *cUnit, OpKind op, int value) argument 255 switch (op) { 286 static ArmLIR *opReg(CompilationUnit *cUnit, OpKind op, int rDestSrc) argument 289 switch (op) { 299 static ArmLIR *opRegRegShift(CompilationUnit *cUnit, OpKind op, int rDestSrc1, argument 304 switch (op) { 415 static ArmLIR *opRegReg(CompilationUnit *cUnit, OpKind op, int rDestSrc1, argument 418 return opRegRegShift(cUnit, op, rDestSrc 421 opRegRegRegShift(CompilationUnit *cUnit, OpKind op, int rDest, int rSrc1, int rSrc2, int shift) argument 485 opRegRegReg(CompilationUnit *cUnit, OpKind op, int rDest, int rSrc1, int rSrc2) argument 491 opRegRegImm(CompilationUnit *cUnit, OpKind op, int rDest, int rSrc1, int value) argument 614 opRegImm(CompilationUnit *cUnit, OpKind op, int rDestSrc1, int value) argument [all...] |
/dalvik/vm/compiler/codegen/arm/ |
H A D | Assemble.cpp | 1553 static u4 getSkeleton(ArmOpcode op) argument 1555 return EncodingMap[op].skeleton; 2646 // Determine whether the mem op is a store or load 2752 // Handle the decoded mem op accordingly 2810 // Determine whether the mem op is a store or load 2902 // Handle the decoded mem op accordingly
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H A D | CodegenDriver.cpp | 265 /* Branch to mem op decode template */ 744 ALOGE("Invalid long arith op"); 778 OpKind op = kOpBkpt; local 789 op = kOpNeg; 793 op = kOpMvn; 798 op = kOpAdd; 802 op = kOpSub; 806 op = kOpMul; 825 op = kOpAnd; 829 op 2278 OpKind op = (OpKind)0; /* Make gcc happy */ local [all...] |
/dalvik/vm/compiler/codegen/mips/ |
H A D | Assemble.cpp | 930 static u4 getSkeleton(MipsOpCode op) argument 932 return EncodingMap[op].skeleton; 2028 // Determine whether the mem op is a store or load 2134 // Handle the decoded mem op accordingly 2192 // Determine whether the mem op is a store or load 2284 // Handle the decoded mem op accordingly
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H A D | CodegenDriver.cpp | 331 /* Branch to mem op decode template */ 798 ALOGE("Invalid long arith op"); 824 OpKind op = kOpBkpt; local 835 op = kOpNeg; 839 op = kOpMvn; 844 op = kOpAdd; 848 op = kOpSub; 852 op = kOpMul; 870 op = kOpAnd; 874 op 2322 OpKind op = (OpKind)0; /* Make gcc happy */ local [all...] |