Searched defs:opcode (Results 201 - 225 of 241) sorted by relevance

12345678910

/external/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp2245 /// getCondFromSETOpc - return condition code of a SET opcode.
2268 /// getCondFromCmovOpc - return condition code of a CMov opcode.
2388 /// getSETFromCond - Return a set opcode for the given condition and
2415 /// getCMovFromCond - Return a cmov opcode for the given condition,
3301 // We decode the condition code from opcode.
3327 // We swap the condition code and synthesize the new opcode.
3331 // Synthesize the new opcode.
4524 static const uint16_t *lookup(unsigned opcode, unsigned domain) { argument
4526 if (ReplaceableInstrs[i][domain-1] == opcode)
4531 static const uint16_t *lookupAVX2(unsigned opcode, unsigne argument
[all...]
/external/llvm/lib/Transforms/Scalar/
H A DGVN.cpp77 uint32_t opcode; member in struct:__anon9088::Expression
81 Expression(uint32_t o = ~2U) : opcode(o) { }
84 if (opcode != other.opcode)
86 if (opcode == ~0U || opcode == ~1U)
96 return hash_combine(Value.opcode, Value.type,
163 e.opcode = I->getOpcode();
184 e.opcode = (C->getOpcode() << 8) | Predicate;
209 e.opcode
[all...]
/external/llvm/lib/VMCore/
H A DInstructions.cpp1978 // order dependent (SetLT f.e.) the opcode is changed.
2106 /// opcode should be used in the elimination. This assumes that there are two
2186 // allowed, use first cast's opcode
2189 // allowed, use second cast's opcode
2294 default: llvm_unreachable("Invalid opcode provided");
2315 default: llvm_unreachable("Invalid opcode provided");
2399 Instruction::CastOps opcode = local
2403 return Create(opcode, C, Ty, Name, InsertBefore);
2413 Instruction::CastOps opcode = local
2417 return Create(opcode,
2427 Instruction::CastOps opcode = local
2440 Instruction::CastOps opcode = local
[all...]
H A DCore.cpp698 static LLVMOpcode map_to_llvmopcode(int opcode) argument
700 switch (opcode) {
/external/mdnsresponder/mDNSShared/
H A Ddnsextd.c767 { vlogmsg = "Request opcode not an update"; goto failure; }
772 { vlogmsg = "Reply opcode not an update response"; goto failure; }
1645 mDNSlocal void FormatLLQOpt(AuthRecord *opt, int opcode, const mDNSOpaque64 *const id, mDNSs32 lease) argument
1654 opt->resrec.rdata->u.opt[0].u.llq.llqOp = opcode;
/external/stressapptest/src/
H A Dworker.cc2905 const int opcode; member in struct:__anon12676
2917 cb.aio_lio_opcode = operations[op].opcode;
/external/v8/src/ia32/
H A Dlithium-ia32.h181 virtual Opcode opcode() const { return LInstruction::k##type; } \
219 virtual Opcode opcode() const = 0;
223 bool Is##type() const { return opcode() == k##type; }
228 // an opcode.
1109 virtual Opcode opcode() const { return LInstruction::kArithmeticD; } function in class:v8::internal::LArithmeticD
1130 virtual Opcode opcode() const { return LInstruction::kArithmeticT; } function in class:v8::internal::LArithmeticT
/external/v8/src/mips/
H A Dassembler-mips.cc502 uint32_t opcode = GetOpcodeField(instr); local
507 return opcode == BEQ ||
508 opcode == BNE ||
509 opcode == BLEZ ||
510 opcode == BGTZ ||
511 opcode == BEQL ||
512 opcode == BNEL ||
513 opcode == BLEZL ||
514 opcode == BGTZL ||
515 (opcode
533 uint32_t opcode = GetOpcodeField(instr); local
545 uint32_t opcode = GetOpcodeField(instr); local
565 uint32_t opcode = GetOpcodeField(instr); local
572 uint32_t opcode = GetOpcodeField(instr); local
853 GenInstrRegister(Opcode opcode, Register rs, Register rt, Register rd, uint16_t sa, SecondaryField func) argument
866 GenInstrRegister(Opcode opcode, Register rs, Register rt, uint16_t msb, uint16_t lsb, SecondaryField func) argument
879 GenInstrRegister(Opcode opcode, SecondaryField fmt, FPURegister ft, FPURegister fs, FPURegister fd, SecondaryField func) argument
893 GenInstrRegister(Opcode opcode, SecondaryField fmt, Register rt, FPURegister fs, FPURegister fd, SecondaryField func) argument
907 GenInstrRegister(Opcode opcode, SecondaryField fmt, Register rt, FPUControlRegister fs, SecondaryField func) argument
922 GenInstrImmediate(Opcode opcode, Register rs, Register rt, int32_t j) argument
933 GenInstrImmediate(Opcode opcode, Register rs, SecondaryField SF, int32_t j) argument
943 GenInstrImmediate(Opcode opcode, Register rs, FPURegister ft, int32_t j) argument
955 GenInstrJump(Opcode opcode, uint32_t address) argument
[all...]
H A Dmacro-assembler-mips.cc5412 uint32_t opcode = Assembler::GetOpcodeField(instr); local
5414 // branch instructions (with opcode being the branch type).
5417 ASSERT(opcode == BEQ ||
5418 opcode == BNE ||
5419 opcode == BLEZ ||
5420 opcode == BGTZ ||
5421 opcode == BEQL ||
5422 opcode == BNEL ||
5423 opcode == BLEZL ||
5424 opcode
[all...]
H A Dlithium-mips.h185 virtual Opcode opcode() const { return LInstruction::k##type; } \
223 virtual Opcode opcode() const = 0;
227 bool Is##type() const { return opcode() == k##type; }
232 // an opcode.
1088 virtual Opcode opcode() const { return LInstruction::kArithmeticD; } function in class:v8::internal::LArithmeticD
1105 virtual Opcode opcode() const { return LInstruction::kArithmeticT; } function in class:v8::internal::LArithmeticT
/external/v8/src/x64/
H A Dassembler-x64.cc571 void Assembler::arithmetic_op(byte opcode, Register reg, const Operand& op) { argument
574 emit(opcode);
579 void Assembler::arithmetic_op(byte opcode, Register reg, Register rm_reg) { argument
581 ASSERT((opcode & 0xC6) == 2);
583 // Swap reg and rm_reg and change opcode operand order.
585 emit(opcode ^ 0x02);
589 emit(opcode);
595 void Assembler::arithmetic_op_16(byte opcode, Register reg, Register rm_reg) { argument
597 ASSERT((opcode & 0xC6) == 2);
599 // Swap reg and rm_reg and change opcode operan
613 arithmetic_op_16(byte opcode, Register reg, const Operand& rm_reg) argument
624 arithmetic_op_32(byte opcode, Register reg, Register rm_reg) argument
640 arithmetic_op_32(byte opcode, Register reg, const Operand& rm_reg) argument
[all...]
H A Dlithium-x64.h186 virtual Opcode opcode() const { return LInstruction::k##type; } \
225 virtual Opcode opcode() const = 0;
229 bool Is##type() const { return opcode() == k##type; }
234 // an opcode.
1087 virtual Opcode opcode() const { return LInstruction::kArithmeticD; } function in class:v8::internal::LArithmeticD
1104 virtual Opcode opcode() const { return LInstruction::kArithmeticT; } function in class:v8::internal::LArithmeticT
/external/bluetooth/bluedroid/bta/dm/
H A Dbta_dm_int.h168 UINT16 opcode; member in struct:__anon420
/external/freetype/src/truetype/
H A Dttinterp.c824 /* Before an opcode is executed, the interpreter verifies that there are */
828 /* For each opcode, the first column gives the number of arguments that */
2408 /* selector :: SROUND opcode */
2428 /* This opcode is reserved, but... */
2873 /* call table defined later below in this source. Each opcode must */
2883 A = (FT_Short)( CUR.opcode & 1 ) << 14; \
2903 A = (FT_Short)( CUR.opcode & 1 ) << 14; \
2923 A = (FT_Short)( CUR.opcode & 1 ) << 14; \
2938 CUR.opcode, \
2950 CUR.opcode, \
7596 FT_Byte opcode = CUR.opcode; local
[all...]
/external/v8/src/arm/
H A Dlithium-arm.h186 virtual Opcode opcode() const { return LInstruction::k##type; } \
224 virtual Opcode opcode() const = 0;
228 bool Is##type() const { return opcode() == k##type; }
233 // an opcode.
1108 virtual Opcode opcode() const { return LInstruction::kArithmeticD; } function in class:v8::internal::LArithmeticD
1125 virtual Opcode opcode() const { return LInstruction::kArithmeticT; } function in class:v8::internal::LArithmeticT
/external/v8/src/
H A Dhydrogen-instructions.h220 virtual Opcode opcode() const { return HValue::k##type; }
560 virtual Opcode opcode() const = 0;
564 bool Is##type() const { return opcode() == k##type; }
567 bool IsPhi() const { return opcode() == kPhi; }
2322 virtual Opcode opcode() const { return HValue::kPhi; } function in class:v8::HPhi
/external/valgrind/main/coregrind/m_debuginfo/
H A Dreaddwarf.c391 VG_(printf)(" Extended opcode %d: End of Sequence\n\n",
399 VG_(printf)(" Extended opcode %d: set Address to 0x%lx\n",
543 /* We only support machines with one opcode per instruction
756 VG_(printf)(" Special opcode %d: advance Address by %d "
924 VG_(printf)(" Unknown opcode %d\n", (Int)op_code);
2661 UChar opcode; local
2712 opcode = *expr++;
2713 switch (opcode) {
2717 sw = (Word)opcode - (Word)DW_OP_lit0;
2726 reg = (Int)opcode
[all...]
/external/webkit/Source/JavaScriptCore/assembler/
H A DSH4Assembler.h1541 void oneShortOp(uint16_t opcode, bool checksize = true, bool isDouble = true) argument
1543 printInstr(opcode, m_buffer.uncheckedSize(), isDouble);
1546 m_buffer.putShortUnchecked(opcode);
H A DX86Assembler.h1683 // In addition to the opcode, the following operand permutations are supported:
1685 // * One register - the low three bits of the RegisterID are added into the opcode.
1693 // The twoByteOp methods plant two-byte Intel instructions sequences (first opcode byte 0x0F).
1695 void oneByteOp(OneByteOpcodeID opcode) argument
1698 m_buffer.putByteUnchecked(opcode);
1701 void oneByteOp(OneByteOpcodeID opcode, RegisterID reg) argument
1705 m_buffer.putByteUnchecked(opcode + (reg & 7));
1708 void oneByteOp(OneByteOpcodeID opcode, int reg, RegisterID rm) argument
1712 m_buffer.putByteUnchecked(opcode);
1716 void oneByteOp(OneByteOpcodeID opcode, in argument
1724 oneByteOp_disp32(OneByteOpcodeID opcode, int reg, RegisterID base, int offset) argument
1732 oneByteOp(OneByteOpcodeID opcode, int reg, RegisterID base, RegisterID index, int scale, int offset) argument
1741 oneByteOp(OneByteOpcodeID opcode, int reg, const void* address) argument
1749 twoByteOp(TwoByteOpcodeID opcode) argument
1756 twoByteOp(TwoByteOpcodeID opcode, int reg, RegisterID rm) argument
1765 twoByteOp(TwoByteOpcodeID opcode, int reg, RegisterID base, int offset) argument
1774 twoByteOp(TwoByteOpcodeID opcode, int reg, RegisterID base, RegisterID index, int scale, int offset) argument
1784 twoByteOp(TwoByteOpcodeID opcode, int reg, const void* address) argument
1800 oneByteOp64(OneByteOpcodeID opcode) argument
1807 oneByteOp64(OneByteOpcodeID opcode, RegisterID reg) argument
1814 oneByteOp64(OneByteOpcodeID opcode, int reg, RegisterID rm) argument
1822 oneByteOp64(OneByteOpcodeID opcode, int reg, RegisterID base, int offset) argument
1830 oneByteOp64_disp32(OneByteOpcodeID opcode, int reg, RegisterID base, int offset) argument
1838 oneByteOp64(OneByteOpcodeID opcode, int reg, RegisterID base, RegisterID index, int scale, int offset) argument
1846 twoByteOp64(TwoByteOpcodeID opcode, int reg, RegisterID rm) argument
1881 oneByteOp8(OneByteOpcodeID opcode, GroupOpcodeID groupOp, RegisterID rm) argument
1889 twoByteOp8(TwoByteOpcodeID opcode, RegisterID reg, RegisterID rm) argument
1898 twoByteOp8(TwoByteOpcodeID opcode, GroupOpcodeID groupOp, RegisterID rm) argument
[all...]
/external/bluetooth/bluedroid/stack/include/
H A Duipc_msg.h60 UINT8 opcode; /* UIPC_OPEN_REQ */ member in struct:__anon1345
67 UINT8 opcode; /* UIPC_OPEN_RESP */ member in struct:__anon1346
78 UINT8 opcode; /* UIPC_CLOSE_REQ */ member in struct:t_uipc_close_req
85 UINT8 opcode; /* UIPC_CLOSE_RSP */ member in struct:t_uipc_close_rsp
92 UINT8 opcode; member in union:__anon1347
247 UINT8 opcode; /* AVDT_SYNC_TO_BTC_LITE_REQ */ member in struct:__anon1350
254 UINT8 opcode; /* AVDT_SYNC_TO_BTC_LITE_RESP */ member in struct:__anon1351
335 UINT8 opcode; /* A2DP_START_REQ */ member in struct:__anon1352
342 UINT8 opcode; /* A2DP_STOP_REQ */ member in struct:__anon1353
348 UINT8 opcode; /* A2DP_SUSPEND_RE member in struct:__anon1354
354 UINT8 opcode; /* A2DP_CLEANUP_REQ */ member in struct:__anon1355
361 UINT8 opcode; /* A2DP_START_RESP, A2DP_STOP_RESP, A2DP_CLEANUP_RESP, A2DP_SUSPEND_RESP */ member in struct:__anon1356
599 UINT8 opcode; /* AUDIO_CODEC_CONFIG_REQ */ member in struct:__anon1363
613 UINT8 opcode; /* AUDIO_CODEC_CONFIG_RESP */ member in struct:__anon1364
619 UINT8 opcode; /* AUDIO_CODEC_SET_BITRATE_REQ */ member in struct:__anon1365
699 UINT8 opcode; /* AUDIO_ROUTE_CONFIG_REQ */ member in struct:__anon1367
710 UINT8 opcode; /* AUDIO_ROUTE_CONFIG_RESP */ member in struct:__anon1368
749 UINT8 opcode; /* AUDIO_MIX_CONFIG_REQ */ member in struct:__anon1372
758 UINT8 opcode; /* AUDIO_MIX_CONFIG_RESP */ member in struct:__anon1373
765 UINT8 opcode; /* AUDIO_BURST_FRAMES_IND */ member in struct:__anon1374
771 UINT8 opcode; /* AUDIO_BURST_END_IND */ member in struct:__anon1375
776 UINT8 opcode; /* AUDIO_CODEC_FLUSH_REQ */ member in struct:__anon1376
781 UINT8 opcode; /* AUDIO_EQ_MODE_CONFIG_REQ */ member in struct:__anon1377
788 UINT8 opcode; /* AUDIO_SCALE_CONFIG_REQ */ member in struct:__anon1378
869 UINT8 opcode; member in union:__anon1385
[all...]
H A Davrc_defs.h57 by the opcode and operand,
61 opcode but cannot respond because the current state
98 #define AVRC_OP_PASS_THRU 0x7C /* panel subunit opcode */
764 UINT8 opcode; /* Op Code (passthrough, vendor, etc) */ member in struct:__anon1087
970 UINT8 opcode; /* Op Code (assigned by AVRC_BldCommand according to pdu) */ member in struct:__anon1105
979 UINT8 opcode; /* Op Code (assigned by AVRC_BldCommand according to pdu) */ member in struct:__anon1106
988 UINT8 opcode; /* Op Code (assigned by AVRC_BldCommand according to pdu) */ member in struct:__anon1107
998 UINT8 opcode; /* Op Code (assigned by AVRC_BldCommand according to pdu) */ member in struct:__anon1108
1008 UINT8 opcode; /* Op Code (assigned by AVRC_BldCommand according to pdu) */ member in struct:__anon1109
1018 UINT8 opcode; /* O member in struct:__anon1110
1029 UINT8 opcode; /* Op Code (assigned by AVRC_BldCommand according to pdu) */ member in struct:__anon1111
1039 UINT8 opcode; /* Op Code (assigned by AVRC_BldCommand according to pdu) */ member in struct:__anon1112
1048 UINT8 opcode; /* Op Code (assigned by AVRC_BldCommand according to pdu) */ member in struct:__anon1113
1058 UINT8 opcode; /* Op Code (assigned by AVRC_BldCommand according to pdu) */ member in struct:__anon1114
1068 UINT8 opcode; /* Op Code (assigned by AVRC_BldCommand according to pdu) */ member in struct:__anon1115
1077 UINT8 opcode; /* Op Code (assigned by AVRC_BldCommand according to pdu) */ member in struct:__anon1116
1086 UINT8 opcode; /* Op Code (assigned by AVRC_BldCommand according to pdu) */ member in struct:__anon1117
1095 UINT8 opcode; /* Op Code (assigned by AVRC_BldCommand according to pdu) */ member in struct:__anon1118
1108 UINT8 opcode; /* Op Code (assigned by AVRC_BldCommand according to pdu) */ member in struct:__anon1119
1119 UINT8 opcode; /* Op Code (assigned by AVRC_BldCommand according to pdu) */ member in struct:__anon1120
1132 UINT8 opcode; /* Op Code (assigned by AVRC_BldCommand according to pdu) */ member in struct:__anon1121
1141 UINT8 opcode; /* Op Code (assigned by AVRC_BldCommand according to pdu) */ member in struct:__anon1122
1152 UINT8 opcode; /* Op Code (assigned by AVRC_BldCommand according to pdu) */ member in struct:__anon1123
1162 UINT8 opcode; /* Op Code (assigned by AVRC_BldCommand according to pdu) */ member in struct:__anon1124
1170 UINT8 opcode; /* Op Code (assigned by AVRC_BldCommand according to pdu) */ member in struct:__anon1125
1209 UINT8 opcode; /* Op Code (copied from avrc_cmd.opcode by AVRC_BldResponse user. invalid one to generate according to pdu) */ member in struct:__anon1127
1220 UINT8 opcode; /* Op Code (copied from avrc_cmd.opcode by AVRC_BldResponse user. invalid one to generate according to pdu) */ member in struct:__anon1128
1230 UINT8 opcode; /* Op Code (copied from avrc_cmd.opcode by AVRC_BldResponse user. invalid one to generate according to pdu) */ member in struct:__anon1129
1240 UINT8 opcode; /* Op Code (copied from avrc_cmd.opcode by AVRC_BldResponse user. invalid one to generate according to pdu) */ member in struct:__anon1130
1250 UINT8 opcode; /* Op Code (copied from avrc_cmd.opcode by AVRC_BldResponse user. invalid one to generate according to pdu) */ member in struct:__anon1131
1260 UINT8 opcode; /* Op Code (copied from avrc_cmd.opcode by AVRC_BldResponse user. invalid one to generate according to pdu) */ member in struct:__anon1132
1270 UINT8 opcode; /* Op Code (copied from avrc_cmd.opcode by AVRC_BldResponse user. invalid one to generate according to pdu) */ member in struct:__anon1133
1313 UINT8 opcode; /* Op Code (copied from avrc_cmd.opcode by AVRC_BldResponse user. invalid one to generate according to pdu) */ member in struct:__anon1137
1323 UINT8 opcode; /* Op Code (copied from avrc_cmd.opcode by AVRC_BldResponse user. invalid one to generate according to pdu) */ member in struct:__anon1138
1332 UINT8 opcode; /* Op Code (copied from avrc_cmd.opcode by AVRC_BldResponse user. invalid one to generate according to pdu) */ member in struct:__anon1139
1345 UINT8 opcode; /* Op Code (copied from avrc_cmd.opcode by AVRC_BldResponse user. invalid one to generate according to pdu) */ member in struct:__anon1140
1356 UINT8 opcode; /* Op Code (copied from avrc_cmd.opcode by AVRC_BldResponse user. invalid one to generate according to pdu) */ member in struct:__anon1141
1365 UINT8 opcode; /* Op Code (copied from avrc_cmd.opcode by AVRC_BldResponse user. invalid one to generate according to pdu) */ member in struct:__anon1142
1375 UINT8 opcode; /* Op Code (copied from avrc_cmd.opcode by AVRC_BldResponse user. invalid one to generate according to pdu) */ member in struct:__anon1143
1385 UINT8 opcode; /* Op Code (copied from avrc_cmd.opcode by AVRC_BldResponse user. invalid one to generate according to pdu) */ member in struct:__anon1144
[all...]
H A Dbtm_api.h94 UINT16 opcode; member in struct:__anon1157
2219 BTM_API extern tBTM_STATUS BTM_VendorSpecificCommand(UINT16 opcode,
/external/elfutils/src/
H A Dreadelf.c4589 /* The opcode base. */
4718 /* Read the opcode. */
4719 unsigned int opcode = *linep++; local
4721 /* Is this a special opcode? */
4722 if (likely (opcode >= opcode_base))
4724 /* Yes. Handling this is quite easy since the opcode value
4727 opcode = (desired line increment - line_base)
4731 + (opcode - opcode_base) % line_range);
4733 * ((opcode - opcode_base)
4742 special opcode
5128 unsigned int opcode = *readp++; local
[all...]
/external/qemu/
H A Dppc-dis.c24 /* ppc.h -- Header file for PowerPC opcode table
45 /* The opcode table is an array of struct powerpc_opcode. */
49 /* The opcode name. */
52 /* The opcode itself. Those bits which will be filled in with
54 unsigned long opcode; member in struct:powerpc_opcode
56 /* The opcode mask. This is used by the disassembler. This is a
58 opcode field, and zeroes indicating those bits which need not
62 /* One bit flags for the opcode. These are used to indicate which
73 /* The table itself is sorted by major opcode number, and is otherwise
169 /* A macro to extract the major opcode fro
5250 const struct powerpc_opcode *opcode; local
[all...]
/external/qemu/target-mips/
H A Dtranslate.c45 /* indirect opcode tables */
117 /* Reserved major opcode */
465 uint32_t opcode; member in struct:DisasContext
507 ctx->pc, ctx->opcode , ## __VA_ARGS__)
516 MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26, \
517 ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \
835 opcode tables. */
1434 switch ((ctx->opcode >> 21) & 0x1f) {
1484 switch ((ctx->opcode >> 2
[all...]

Completed in 634 milliseconds

12345678910