| /dalvik/vm/compiler/codegen/arm/ |
| H A D | ArchFactory.cpp | 95 static TGT_LIR *genBoundsCheck(CompilationUnit *cUnit, int rIndex, argument
98 return genRegRegCheck(cUnit, kArmCondCs, rIndex, rBound, dOffset,
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| /dalvik/vm/compiler/codegen/mips/ |
| H A D | CodegenFactory.cpp | 316 static MipsLIR *genBoundsCheck(CompilationUnit *cUnit, int rIndex, argument
319 return genRegRegCheck(cUnit, kMipsCondCs, rIndex, rBound, dOffset,
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| /dalvik/vm/compiler/codegen/arm/Thumb/ |
| H A D | Factory.cpp | 470 int rIndex, int rDest, int scale, OpSize size)
475 int rNewIndex = rIndex;
479 first = opRegRegImm(cUnit, kOpLsl, rNewIndex, rIndex, scale);
513 int rIndex, int rSrc, int scale, OpSize size)
518 int rNewIndex = rIndex;
521 first = opRegRegImm(cUnit, kOpLsl, rNewIndex, rIndex, scale);
469 loadBaseIndexed(CompilationUnit *cUnit, int rBase, int rIndex, int rDest, int scale, OpSize size) argument
512 storeBaseIndexed(CompilationUnit *cUnit, int rBase, int rIndex, int rSrc, int scale, OpSize size) argument
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| /dalvik/vm/compiler/codegen/mips/Mips32/ |
| H A D | Factory.cpp | 422 int rIndex, int rDest, int scale, OpSize size)
441 first = newLIR3(cUnit, kMipsAddu, tReg , rBase, rIndex);
443 first = opRegRegImm(cUnit, kOpLsl, tReg, rIndex, scale);
484 int rIndex, int rSrc, int scale, OpSize size)
489 int rNewIndex = rIndex;
504 first = newLIR3(cUnit, kMipsAddu, tReg , rBase, rIndex);
506 first = opRegRegImm(cUnit, kOpLsl, tReg, rIndex, scale);
421 loadBaseIndexed(CompilationUnit *cUnit, int rBase, int rIndex, int rDest, int scale, OpSize size) argument
483 storeBaseIndexed(CompilationUnit *cUnit, int rBase, int rIndex, int rSrc, int scale, OpSize size) argument
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| /dalvik/vm/compiler/codegen/arm/Thumb2/ |
| H A D | Factory.cpp | 714 int rIndex, int rDest, int scale, OpSize size)
716 bool allLowRegs = LOWREG(rBase) && LOWREG(rIndex) && LOWREG(rDest);
736 newLIR4(cUnit, kThumb2AddRRR, regPtr, rBase, rIndex,
739 opRegRegReg(cUnit, kOpAdd, regPtr, rBase, rIndex);
766 load = newLIR3(cUnit, opcode, rDest, rBase, rIndex);
768 load = newLIR4(cUnit, opcode, rDest, rBase, rIndex, scale);
778 int rIndex, int rSrc, int scale, OpSize size)
780 bool allLowRegs = LOWREG(rBase) && LOWREG(rIndex) && LOWREG(rSrc);
800 newLIR4(cUnit, kThumb2AddRRR, regPtr, rBase, rIndex,
803 opRegRegReg(cUnit, kOpAdd, regPtr, rBase, rIndex);
713 loadBaseIndexed(CompilationUnit *cUnit, int rBase, int rIndex, int rDest, int scale, OpSize size) argument
777 storeBaseIndexed(CompilationUnit *cUnit, int rBase, int rIndex, int rSrc, int scale, OpSize size) argument
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