| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMAsmBackend.cpp | 42 const MCSubtargetInfo* STI; member in class:__anon8875::ARMAsmBackend
46 : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")),
50 delete STI;
56 return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0;
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| H A D | ARMMCCodeEmitter.cpp | 41 const MCSubtargetInfo &STI; member in class:__anon8880::ARMMCCodeEmitter
47 : MCII(mcii), STI(sti), CTX(ctx) {
54 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
57 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0;
60 Triple TT(STI.getTargetTriple());
342 const MCSubtargetInfo &STI,
344 return new ARMMCCodeEmitter(MCII, STI, Ctx);
340 createARMMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx) argument
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| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| H A D | PPCMCTargetDesc.cpp | 113 const MCSubtargetInfo &STI) {
108 createPPCMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
|
| /external/llvm/tools/llvm-objdump/ |
| H A D | llvm-objdump.cpp | 250 OwningPtr<const MCSubtargetInfo> STI(
253 if (!STI) {
259 TheTarget->createMCDisassembler(*STI));
279 AsmPrinterVariant, *AsmInfo, *MII, *MRI, *STI));
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| H A D | MachODump.cpp | 259 STI(TheTarget->createMCSubtargetInfo(TripleName, "", ""));
260 OwningPtr<const MCDisassembler> DisAsm(TheTarget->createMCDisassembler(*STI));
265 *MRI, *STI));
267 if (!InstrAnalysis || !AsmInfo || !STI || !DisAsm || !IP) {
|
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| H A D | AsmPrinterInlineAsm.cpp | 123 STI(TM.getTarget().createMCSubtargetInfo(TM.getTargetTriple(),
127 TAP(TM.getTarget().createMCAsmParser(*STI, *Parser));
|
| /external/llvm/lib/Target/ARM/ |
| H A D | MLxExpansionPass.cpp | 318 const ARMSubtarget *STI = &Fn.getTarget().getSubtarget<ARMSubtarget>(); local
319 isA9 = STI->isCortexA9();
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| H A D | Thumb2InstrInfo.cpp | 32 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI) argument
33 : ARMBaseInstrInfo(STI), RI(*this, STI) {
|
| H A D | Thumb1FrameLowering.cpp | 103 if (STI.isTargetIOS()) {
149 if (STI.isTargetELF() && hasFP(MF))
|
| H A D | ARMBaseInstrInfo.h | 35 explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
|
| H A D | Thumb2SizeReduction.cpp | 138 const ARMSubtarget *STI; member in class:__anon8885::Thumb2SizeReduce
220 if (!STI->avoidCPSRPartialUpdate())
932 STI = &TM.getSubtarget<ARMSubtarget>();
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| H A D | ARMLoadStoreOptimizer.cpp | 67 const ARMSubtarget *STI; member in struct:__anon8843::ARMLoadStoreOpt
1110 bool Errata602117 = EvenReg == BaseReg && STI->isCortexM3();
1424 STI = &TM.getSubtarget<ARMSubtarget>();
1454 const ARMSubtarget *STI; member in struct:__anon8844::ARMPreAllocLoadStoreOpt
1484 STI = &Fn.getTarget().getSubtarget<ARMSubtarget>();
1568 if (!STI->hasV5TEOps())
1597 unsigned ReqAlign = STI->hasV6Ops()
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| H A D | ARMConstantIslandPass.cpp | 260 const ARMSubtarget *STI; member in class:__anon8834::ARMConstantIslands
386 STI = &MF->getTarget().getSubtarget<ARMSubtarget>();
470 if (isThumb2 && !STI->prefers32BitThumb())
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| H A D | ARMExpandPseudoInsts.cpp | 44 const ARMSubtarget *STI; member in class:__anon8835::ARMExpandPseudo
623 if (!STI->hasV6T2Ops() &&
1286 STI = &TM.getSubtarget<ARMSubtarget>();
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 38 MCSubtargetInfo &STI; member in class:__anon8936::MipsAsmParser
79 return (STI.getFeatureBits() & Mips::FeatureMips64) != 0;
83 return (STI.getFeatureBits() & Mips::FeatureFP64Bit) != 0;
106 : MCTargetAsmParser(), STI(sti), Parser(parser) {
108 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
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| /external/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 94 ARMDisassembler(const MCSubtargetInfo &STI) : argument
95 MCDisassembler(STI) {
119 ThumbDisassembler(const MCSubtargetInfo &STI) : argument
120 MCDisassembler(STI) {
390 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { argument
391 return new ARMDisassembler(STI);
394 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { argument
395 return new ThumbDisassembler(STI);
415 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
432 Address, this, STI);
[all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86MCCodeEmitter.cpp | 34 const MCSubtargetInfo &STI; member in class:__anon9009::X86MCCodeEmitter
39 : MCII(mcii), STI(sti), Ctx(ctx) {
46 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
51 return (STI.getFeatureBits() & X86::Mode64Bit) == 0;
143 const MCSubtargetInfo &STI,
145 return new X86MCCodeEmitter(MCII, STI, Ctx);
|
| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonAsmPrinter.cpp | 302 const MCSubtargetInfo &STI) {
297 createHexagonMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
|
| H A D | HexagonFrameLowering.cpp | 191 if (STI.hasV4TOps() && MBBI->getOpcode() == Hexagon::JMPR
|
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsMCTargetDesc.cpp | 122 const MCSubtargetInfo &STI) {
117 createMipsMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
|
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| H A D | ARMInstPrinter.h | 27 const MCRegisterInfo &MRI, const MCSubtargetInfo &STI);
|
| /external/clang/lib/Sema/ |
| H A D | SemaStmtAsm.cpp | 511 STI(TheTarget->createMCSubtargetInfo(TT, "", ""));
526 TargetParser(TheTarget->createMCAsmParser(*STI, *Parser));
566 TheTarget->createMCInstPrinter(1, *MAI, *MII, *MRI, *STI);
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| /external/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86AsmParser.cpp | 34 MCSubtargetInfo &STI; member in class:__anon8981::X86AsmParser
93 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
96 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(X86::Mode64Bit));
110 : MCTargetAsmParser(), STI(sti), Parser(parser) {
113 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
|
| /external/llvm/lib/Target/MBlaze/Disassembler/ |
| H A D | MBlazeDisassembler.cpp | 718 const MCSubtargetInfo &STI) {
719 return new MBlazeDisassembler(STI);
717 createMBlazeDisassembler(const Target &T, const MCSubtargetInfo &STI) argument
|
| /external/llvm/tools/lto/ |
| H A D | LTOModule.cpp | 808 STI(T.createMCSubtargetInfo(_target->getTargetTriple(),
811 OwningPtr<MCTargetAsmParser> TAP(T.createMCAsmParser(*STI, *Parser.get()));
|