| /dalvik/vm/compiler/codegen/x86/libenc/ |
| H A D | enc_prvt.h | 140 #define AX {OpndKind_GPReg, OpndSize_16, OpndExt_Any, RegName_AX}
152 #define DX {OpndKind_GPReg, OpndSize_16, OpndExt_Any, RegName_DX}
169 #define r16 {OpndKind_GPReg, OpndSize_16, OpndExt_Any, RegName_Null}
176 #define r_m16 {(OpndKind)(OpndKind_GPReg|OpndKind_Mem), OpndSize_16, OpndExt_Any, RegName_Null}
180 #define r_m16s {(OpndKind)(OpndKind_GPReg|OpndKind_Mem), OpndSize_16, OpndExt_Signed, RegName_Null}
184 #define r_m16u {(OpndKind)(OpndKind_GPReg|OpndKind_Mem), OpndSize_16, OpndExt_Zero, RegName_Null}
191 #define m16 {OpndKind_Mem, OpndSize_16, OpndExt_Any, RegName_Null}
199 #define imm16 {OpndKind_Imm, OpndSize_16, OpndExt_Any, RegName_Null}
203 #define imm16s {OpndKind_Imm, OpndSize_16, OpndExt_Signed, RegName_Null}
207 #define imm16u {OpndKind_Imm, OpndSize_16, OpndExt_Zer
[all...] |
| H A D | enc_defs.h | 207 RegName_AX=REGNAME(OpndKind_GPReg,OpndSize_16,0),
208 RegName_CX=REGNAME(OpndKind_GPReg,OpndSize_16,1),
209 RegName_DX=REGNAME(OpndKind_GPReg,OpndSize_16,2),
210 RegName_BX=REGNAME(OpndKind_GPReg,OpndSize_16,3),
211 RegName_SP=REGNAME(OpndKind_GPReg,OpndSize_16,4),
212 RegName_BP=REGNAME(OpndKind_GPReg,OpndSize_16,5),
213 RegName_SI=REGNAME(OpndKind_GPReg,OpndSize_16,6),
214 RegName_DI=REGNAME(OpndKind_GPReg,OpndSize_16,7),
217 RegName_R8S = REGNAME(OpndKind_GPReg,OpndSize_16,8),
218 RegName_R9S = REGNAME(OpndKind_GPReg,OpndSize_16,
[all...] |
| H A D | encoder.cpp | 120 OpndSize_8, OpndSize_16, OpndSize_32, OpndSize_64, OpndSize_Any
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| H A D | enc_base.h | 355 * @brief Creates immediate operand of OpndSize_16.
358 m_kind(OpndKind_Imm), m_size(OpndSize_16), m_ext(ext), m_imm64(ival)
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| H A D | enc_defs_ext.h | 42 OpndSize_16 = 0x02, enumerator in enum:OpndSize
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| H A D | dec_base.cpp | 257 opnd_size = OpndSize_16;
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| H A D | enc_base.cpp | 51 2, // OpndSize_16 = 0x2,
881 { "Sz16", OpndSize_16 },
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| H A D | encoder.inl | 739 EncoderBase::Operands args(EncoderBase::Operand(OpndSize_16, pop, OpndExt_Zero));
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| H A D | enc_tabl.cpp | 1883 else if (sz==OpndSize_16) {imm_encode = iw; coff_encode=cw;}
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| /dalvik/vm/compiler/codegen/x86/ |
| H A D | LowerJump.cpp | 91 if(immSize == OpndSize_16) { //-2^16 to 2^16-1
420 if(target-MIN_JCC_SIZE < 32768 && target-MAX_JCC_SIZE >= -32768) return OpndSize_16;
431 if(size == OpndSize_16) return 4;
436 if(size == OpndSize_16) return 5;
445 if(size == OpndSize_16) return 4;
481 *immSize = OpndSize_16;
495 *immSize = OpndSize_16;
508 *immSize = OpndSize_16;
890 *size = OpndSize_16;
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| H A D | LowerGetPut.cpp | 73 movez_mem_disp_scale_to_reg(OpndSize_16, 1, false, offArrayObject_contents, 2, false, 2, 4, false);
76 moves_mem_disp_scale_to_reg(OpndSize_16, 1, false, offArrayObject_contents, 2, false, 2, 4, false);
228 move_reg_to_mem_disp_scale(OpndSize_16, 4, false, 1, false, offArrayObject_contents, 2, false, 2);
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| H A D | LowerAlu.cpp | 228 alu_binary_imm_mem(OpndSize_16, or_opc, 0xc00, 0, PhysicalReg_ESP, true);
230 alu_binary_imm_mem(OpndSize_16, xor_opc, 0xc00, 0, PhysicalReg_ESP, true);
309 alu_binary_imm_mem(OpndSize_16, or_opc, 0xc00, 0, PhysicalReg_ESP, true);
311 alu_binary_imm_mem(OpndSize_16, xor_opc, 0xc00, 0, PhysicalReg_ESP, true);
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| H A D | LowerInvoke.cpp | 765 movez_mem_to_reg(OpndSize_16, offMethod_registersSize, PhysicalReg_ECX, true, P_SCRATCH_1, true); //regSize
773 movez_mem_to_reg(OpndSize_16, offMethod_outsSize, PhysicalReg_ECX, true, P_SCRATCH_2, true); //outsSize
1066 movez_mem_disp_scale_to_reg(OpndSize_16, 5, false, 0, 1, false, 2,
1078 movez_mem_to_reg(OpndSize_16, 0, 5, false, 6, false);
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| H A D | LowerHelper.cpp | 28 OpndSize can be OpndSize_8, OpndSize_16, OpndSize_32, OpndSize_64
817 dump_mem(m, ATOM_NORMAL, OpndSize_16, disp, base_reg, isBasePhysical);
825 dump_mem(m, ATOM_NORMAL, OpndSize_16, disp, base_reg, isBasePhysical);
1138 dump_reg_reg(m, ATOM_NORMAL, OpndSize_16, reg1, isPhysical1, reg2, isPhysical2, LowOpndRegType_gp);
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