Searched refs:OpndSize_64 (Results 1 - 16 of 16) sorted by relevance

/dalvik/vm/compiler/codegen/x86/
H A DLowerMove.cpp70 get_virtual_reg(vB, OpndSize_64, 1, false);
71 set_virtual_reg(vA, OpndSize_64, 1, false);
81 get_virtual_reg(vB, OpndSize_64, 1, false);
82 set_virtual_reg(vA, OpndSize_64, 1, false);
92 get_virtual_reg(vB, OpndSize_64, 1, false);
93 set_virtual_reg(vA, OpndSize_64, 1, false);
124 get_return_value(OpndSize_64, 1, false);
125 set_virtual_reg(vA, OpndSize_64, 1, false);
H A DLowerAlu.cpp60 get_virtual_reg(vB, OpndSize_64, 1, false);
61 alu_binary_reg_reg(OpndSize_64, xor_opc, 2, false, 2, false);
62 alu_binary_reg_reg(OpndSize_64, sub_opc, 1, false, 2, false);
63 set_virtual_reg(vA, OpndSize_64, 2, false);
73 get_virtual_reg(vB, OpndSize_64, 1, false);
74 load_global_data_API("64bits", OpndSize_64, 2, false);
75 alu_binary_reg_reg(OpndSize_64, andn_opc, 2, false, 1, false);
76 set_virtual_reg(vA, OpndSize_64, 1, false);
101 get_virtual_reg(vB, OpndSize_64, 1, false);
102 load_global_data_API("doubNeg", OpndSize_64,
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H A DLowerGetPut.cpp70 move_mem_disp_scale_to_reg(OpndSize_64, 1, false, offArrayObject_contents, 2, false, 8, 1, false);
85 set_virtual_reg(vA, OpndSize_64, 1, false);
218 get_virtual_reg(vA, OpndSize_64, 1, false);
226 move_reg_to_mem_disp_scale(OpndSize_64, 1, false, 1, false, offArrayObject_contents, 2, false, 8);
497 move_mem_scale_to_reg(OpndSize_64, 7, false, 8, false, 1, 1, false); //access field
498 set_virtual_reg(vA, OpndSize_64, 1, false);
507 get_virtual_reg(vA, OpndSize_64, 1, false);
512 move_reg_to_mem(OpndSize_64, 1, false, -12, PhysicalReg_ESP, true); //1st argument
519 move_reg_to_mem_scale(OpndSize_64, 1, false, 7, false, 8, false, 1);
692 move_mem_to_reg(OpndSize_64, offStaticField_valu
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H A DLowerReturn.cpp139 get_virtual_reg(vA, OpndSize_64, 1, false);
142 set_return_value(OpndSize_64, 1, false);
H A DLowerHelper.cpp28 OpndSize can be OpndSize_8, OpndSize_16, OpndSize_32, OpndSize_64
160 return size == OpndSize_64 ? LowOpndRegType_xmm : LowOpndRegType_gp;
324 reg-reg2, size==OpndSize_64, stream);
831 assert(srcSize == OpndSize_32 && dstSize == OpndSize_64);
912 else if(size != OpndSize_64) {
919 else if(size == OpndSize_64) {
965 return compare_VR_reg_all(OpndSize_64, vA, reg, isPhysical, m);
976 if(size != OpndSize_64) {
1053 if(size != OpndSize_64) {
1058 if((isConst == 1 || isConst == 3) && size == OpndSize_64) {
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H A DAnalysisO1.cpp92 if((type & MASK_FOR_TYPE) == LowOpndRegType_xmm) return OpndSize_64;
93 if((type & MASK_FOR_TYPE) == LowOpndRegType_fs) return OpndSize_64;
120 if(getRegSize(tA) == OpndSize_64 && getRegSize(tB) == OpndSize_32 && regA == regB) return OVERLAP_B_COVER_LOW_OF_A;
121 if(getRegSize(tA) == OpndSize_64 && getRegSize(tB) == OpndSize_32 && regB == regA + 1) return OVERLAP_B_COVER_HIGH_OF_A;
122 if(getRegSize(tA) == OpndSize_32 && getRegSize(tB) == OpndSize_64 && (regA == regB || regA == regB+1)) return OVERLAP_B_COVER_A;
123 if(getRegSize(tB) == OpndSize_64 && getRegSize(tA) == OpndSize_64 && regA == regB+1) return OVERLAP_B_COVER_LOW_OF_A;
124 if(getRegSize(tB) == OpndSize_64 && getRegSize(tA) == OpndSize_64 && regB == regA+1) return OVERLAP_B_COVER_HIGH_OF_A;
132 if(getRegSize(tA) == OpndSize_64
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H A DBytecodeVisitor.cpp462 if(constVRTable[k].regNum == regNum + 1 && size == OpndSize_64) {
471 if(size == OpndSize_64 && indexH >= 0) {
487 if(constVRTable[k].regNum == regNum + 1 && size == OpndSize_64) {
499 if(size == OpndSize_64) {
591 setVRToConst(vA, OpndSize_64, tmpValue);
1096 setVRToConst(vA, OpndSize_64, tmpValue);
1119 setVRToConst(vA, OpndSize_64, tmpValue);
1144 setVRToConst(vA, OpndSize_64, tmpValue);
1166 setVRToConst(vA, OpndSize_64, tmpValue);
/dalvik/vm/compiler/codegen/x86/libenc/
H A Denc_prvt.h143 #define RAX {OpndKind_GPReg, OpndSize_64, OpndExt_Any, RegName_RAX }
149 #define RCX {OpndKind_GPReg, OpndSize_64, OpndExt_Any, RegName_RCX}
155 #define RDX { OpndKind_GPReg, OpndSize_64, OpndExt_Any, RegName_RDX }
160 #define RSI { OpndKind_GPReg, OpndSize_64, OpndExt_Any, RegName_RSI }
165 #define RDI { OpndKind_GPReg, OpndSize_64, OpndExt_Any, RegName_RDI }
172 #define r64 { OpndKind_GPReg, OpndSize_64, OpndExt_Any, RegName_Null }
193 #define m64 {OpndKind_Mem, OpndSize_64, OpndExt_Any, RegName_Null}
195 #define r_m64 { (OpndKind)(OpndKind_GPReg|OpndKind_Mem), OpndSize_64, OpndExt_Any, RegName_Null }
211 #define imm64 {OpndKind_Imm, OpndSize_64, OpndExt_Any, RegName_Null }
220 #define moff64 {OpndKind_Imm, OpndSize_64, OpndExt_An
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H A Denc_defs.h168 RegName_RAX = REGNAME(OpndKind_GPReg,OpndSize_64,0),
169 RegName_RCX = REGNAME(OpndKind_GPReg,OpndSize_64,1),
170 RegName_RDX = REGNAME(OpndKind_GPReg,OpndSize_64,2),
171 RegName_RBX = REGNAME(OpndKind_GPReg,OpndSize_64,3),
172 RegName_RSP = REGNAME(OpndKind_GPReg,OpndSize_64,4),
173 RegName_RBP = REGNAME(OpndKind_GPReg,OpndSize_64,5),
174 RegName_RSI = REGNAME(OpndKind_GPReg,OpndSize_64,6),
175 RegName_RDI = REGNAME(OpndKind_GPReg,OpndSize_64,7),
177 RegName_R8 = REGNAME(OpndKind_GPReg,OpndSize_64,8),
178 RegName_R9 = REGNAME(OpndKind_GPReg,OpndSize_64,
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H A Ddec_base.cpp217 okind = ((opndDesc2.kind & OpndKind_XMMReg) || opndDesc2.size==OpndSize_64) ? OpndKind_XMMReg : OpndKind_GPReg;
222 okind = ((opndDesc.kind & OpndKind_XMMReg) || opndDesc.size==OpndSize_64) ? OpndKind_XMMReg : OpndKind_GPReg;
345 opnd = EncoderBase::Operand(OpndSize_64, ival);
477 OpndKind okind = ((opndDesc.kind & OpndKind_XMMReg) || opndDesc.size == OpndSize_64) ? OpndKind_XMMReg : OpndKind_GPReg;
H A Dencoder.cpp120 OpndSize_8, OpndSize_16, OpndSize_32, OpndSize_64, OpndSize_Any
H A Denc_base.h684 return (size <= OpndSize_64) ? size_hash[size] : 0xFF;
696 static const unsigned char size_hash[OpndSize_64+1];
H A Denc_defs_ext.h44 OpndSize_64 = 0x08, enumerator in enum:OpndSize
H A Denc_base.cpp47 const unsigned char EncoderBase::size_hash[OpndSize_64+1] = {
57 0, // OpndSize_64 = 0x8,
883 { "Sz64", OpndSize_64 },
H A Denc_wrapper.cpp397 add_fp(args, reg, size == OpndSize_64/*is_double*/);
411 add_fp(args, reg, size == OpndSize_64/*is_double*/);
H A Denc_tabl.cpp1885 else if (sz==OpndSize_64) {imm_encode = io; coff_encode=0xCC; }

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