| /external/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 200 /// like ADDC/SUBC, which indicate the carry result is always false.
207 ADDC, SUBC, enumerator in enum:llvm::ISD::NodeType
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| H A D | SelectionDAG.h | 929 case ISD::ADDC:
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| /external/llvm/lib/Target/MBlaze/ |
| H A D | MBlazeDelaySlotFiller.cpp | 193 op == MBlaze::ADDC || op == MBlaze::ADDIC ||
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 80 ADDC, // Add with carry enumerator in enum:llvm::ARMISD::NodeType
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| H A D | ARMISelLowering.cpp | 572 setTargetDAGCombine(ISD::ADDC);
617 setOperationAction(ISD::ADDC, MVT::i32, Custom);
916 case ARMISD::ADDC: return "ARMISD::ADDC";
5153 case ISD::ADDC: Opc = ARMISD::ADDC; break;
5258 case ISD::ADDC:
7267 // If we find this pattern, we can replace the U/SMUL_LOHI, ADDC, and ADDE by
7272 // ADDC | hiAdd
7277 assert(AddcNode->getOpcode() == ISD::ADDC
[all...] |
| /external/qemu/tcg/ppc/ |
| H A D | tcg-target.c | 347 #define ADDC XO31( 10) macro
1616 tcg_out32 (s, ADDC | TAB (0, args[2], args[4]));
1621 tcg_out32 (s, ADDC | TAB (args[0], args[2], args[4]));
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 199 case ISD::ADDC: return "addc";
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| H A D | LegalizeIntegerTypes.cpp | 1146 case ISD::ADDC:
1280 TLI.isOperationLegalOrCustom(ISD::ADDC,
1285 Lo = DAG.getNode(ISD::ADDC, DL, VTList, LoOps, 2);
1523 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1525 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1530 ISD::ADDC : ISD::SUBC,
1536 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1584 if (N->getOpcode() == ISD::ADDC) {
1585 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
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| H A D | DAGCombiner.cpp | 1092 case ISD::ADDC: return visitADDC(N);
1544 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1584 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N0, N1);
2738 APInt ADDC = ADDI->getAPIntValue(); local
2739 if (!TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
2748 ADDC |= Mask;
2749 if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
2752 N0.getOperand(0), DAG.getConstant(ADDC, VT));
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| H A D | SelectionDAG.cpp | 3138 case ISD::ADDC:
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| /external/llvm/lib/Target/Mips/ |
| H A D | MipsISelDAGToDAG.cpp | 416 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
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| H A D | MipsISelLowering.cpp | 335 // ADDENode's second operand must be a flag output of an ADDC node in order
339 if (ADDCNode->getOpcode() != ISD::ADDC)
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| /external/llvm/lib/Target/MBlaze/Disassembler/ |
| H A D | MBlazeDisassembler.cpp | 40 MBlaze::ADD, MBlaze::RSUB, MBlaze::ADDC, MBlaze::RSUBC, //00,01,02,03
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| /external/qemu/tcg/ppc64/ |
| H A D | tcg-target.c | 337 #define ADDC XO31( 10) macro
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| /external/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 88 setOperationAction(ISD::ADDC, MVT::i32, Expand);
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| /external/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 318 case ISD::ADDC:
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| H A D | X86ISelLowering.cpp | 364 setOperationAction(ISD::ADDC, VT, Custom);
11249 case ISD::ADDC: Opc = X86ISD::ADD; break;
11330 case ISD::ADDC:
11393 case ISD::ADDC:
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