Searched refs:ADDiu (Results 1 - 6 of 6) sorted by relevance
/external/llvm/lib/Target/Mips/ |
H A D | MipsAnalyzeImmediate.cpp | 32 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL)); 56 // A single ADDiu will do if RemSize <= 16. 58 AddInstr(SeqLs, Inst(ADDiu, MaskedImm)); 71 // instruction is an ADDiu or ORi. In that case, do not call GetInstSeqLsORi. 79 // Replace a ADDiu & SLL pair with a LUi. 81 // ADDiu 0x0111 86 // Check if the first two instructions are ADDiu and SLL and the shift amount 88 if ((Seq.size() < 2) || (Seq[0].Opc != ADDiu) || 92 // Sign-extend and shift operand of ADDiu and see if it still fits in 16-bit. 130 ADDiu [all...] |
H A D | MipsAnalyzeImmediate.h | 26 /// instruction in the sequence must be an ADDiu if LastInstrIsADDiu is 35 /// GetInstSeqLsADDiu - Get instrucion sequences which end with an ADDiu to 50 /// ReplaceADDiuSLLWithLUi - Replace an ADDiu & SLL pair with a LUi. 58 unsigned ADDiu, ORi, SLL, LUi; member in class:llvm::MipsAnalyzeImmediate
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H A D | MipsLongBranch.cpp | 282 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) 292 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::AT) 299 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) 382 BuildMI(MBB, I, DL, TII->get(Mips::ADDiu), Mips::V0)
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H A D | MipsISelDAGToDAG.cpp | 177 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0) 193 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1) 228 if ((MI.getOpcode() == Mips::ADDiu) && 522 // instructions (ADDiu, ORI and SLL) in that it does not have a register
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H A D | MipsSEInstrInfo.cpp | 258 unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu; local 261 BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount); 290 // instructions (ADDiu, ORI and SLL) in that it does not have a register
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H A D | MipsISelLowering.cpp | 1192 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2) 1435 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2)
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