Searched refs:CSR5 (Results 1 - 3 of 3) sorted by relevance
/external/grub/netboot/ |
H A D | otulip.c | 57 CSR0=0, CSR1=0x08, CSR2=0x10, CSR3=0x18, CSR4=0x20, CSR5=0x28, enumerator in enum:tulip_offsets
|
H A D | davicom.c | 64 CSR0=0, CSR1=0x08, CSR2=0x10, CSR3=0x18, CSR4=0x20, CSR5=0x28, 63 CSR0=0, CSR1=0x08, CSR2=0x10, CSR3=0x18, CSR4=0x20, CSR5=0x28, enumerator in enum:davicom_offsets
|
H A D | tulip.c | 291 CSR0=0, CSR1=0x08, CSR2=0x10, CSR3=0x18, CSR4=0x20, CSR5=0x28, 296 /* The bits in the CSR5 status registers, mostly interrupt sources. */ 1273 if (inl(ioaddr + CSR5) == 0xFFFFFFFF) { 1643 } else if (inl(ioaddr + CSR5) & TPLnkPass) 290 CSR0=0, CSR1=0x08, CSR2=0x10, CSR3=0x18, CSR4=0x20, CSR5=0x28, enumerator in enum:tulip_offsets
|
Completed in 71 milliseconds