Searched refs:L2 (Results 1 - 25 of 73) sorted by relevance

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/external/llvm/test/MC/MachO/
H A Drelax-jumps.s21 jb L2
23 jg L2
25 jae L2
29 L2: label
H A Drelax-recompute-align.s29 jle L2
35 L2: label
H A Ddarwin-x86_64-diff-relocs.s45 jmp L2
50 // jmp L2 - _g3
74 movl %eax,L2(%rip)
81 // movl %eax,L2 - _g2(%rip)
94 L2: label
98 .quad L2
101 .quad L2 - _g2
H A Dx86_32-symbols.s10 L2: label
/external/clang/include/clang/Basic/
H A DLinkage.h63 inline Linkage minLinkage(Linkage L1, Linkage L2) { argument
64 return L1 < L2? L1 : L2;
/external/clang/test/CodeGen/
H A Dindirect-goto.c4 void *addrs[] = { &&L1, &&L2, &&L3, &&L4, &&L5 };
11 L2: res *= 3;
17 static const void *addrs[] = { &&L1, &&L2, &&L3, &&L4, &&L5 };
24 L2: res *= 3;
/external/clang/test/CodeGenCXX/
H A Dmangle-local-classes-nested.cpp17 void L2() { function in struct:S
32 S().L2();
36 void L2() { function in struct:S
51 S().L2();
/external/clang/test/Sema/
H A Dscope-check.c61 goto L2; // expected-error {{goto into protected scope}}
64 L2:;
138 L2: ;
148 &&L2,
161 goto L2; // expected-error {{goto into protected scope}}
163 L2:
186 goto L2;
187 L2:
221 static const void *addrs[] = { &&L1, &&L2 };
228 L2
[all...]
H A Dwarn-duplicate-enum.c76 L2 = L1, enumerator in enum:__anon4606
77 L3 = L2
H A Dstatements.c19 int test5() { return ({L1: L2: L3: 5;}); }
/external/clang/test/SemaCXX/
H A Dreturn-noreturn.cpp34 switch (x) default: L1: L2: case 4: pr6884_abort_struct();
37 switch (x) default: L1: { L2: case 4: pr6884_abort_struct(); }
40 switch (x) default: L1: L2: case 4: { pr6884_abort_struct(); }
63 switch (x) default: L1: L2: case 4: pr6884_abort_struct();
67 switch (x) default: L1: { L2: case 4: pr6884_abort_struct(); }
71 switch (x) default: L1: L2: case 4: { pr6884_abort_struct(); }
90 switch (x) default: L1: L2: case 4: pr6884_abort_struct a;
94 switch (x) default: L1: { L2: case 4: pr6884_abort_struct a; }
98 switch (x) default: L1: L2: case 4: { pr6884_abort_struct a; }
H A Dwarn-unique-enum.cpp26 L1 = 0x8000000000000000ULL, L2 = 0x0000000000000001ULL enumerator in enum:L
/external/oprofile/events/i386/westmere/
H A Dunit_masks58 0x01 l1d_l2 Cycles L1D and L2 locked
119 0x01 i_state L1 writebacks to L2 in I state (misses)
120 0x02 s_state L1 writebacks to L2 in S state
121 0x04 e_state L1 writebacks to L2 in E state
122 0x08 m_state L1 writebacks to L2 in M state
123 0x0f mesi All L1 writebacks to L2
130 0x01 demand_i_state L2 data demand loads in I state (misses)
131 0x02 demand_s_state L2 data demand loads in S state
132 0x04 demand_e_state L2 data demand loads in E state
133 0x08 demand_m_state L2 dat
[all...]
/external/llvm/test/MC/MachO/ARM/
H A Dthumb2-movw-fixup.s12 movw r12, :lower16:L2
13 movt r12, :upper16:L2
18 L2: .long 0 label
/external/oprofile/events/i386/nehalem/
H A Dunit_masks46 0x08 remote_cache_local_home_hit Counts number of memory load instructions retired where the memory reference missed the L1, L2 and LLC caches and HIT in a remote socket's cache
47 0x10 remote_dram Counts number of memory load instructions retired where the memory reference missed the L1, L2 and LLC caches and was remotely homed
48 0x20 local_dram Counts number of memory load instructions retired where the memory reference missed the L1, L2 and LLC caches and required a local socket memory reference
81 0x01 ld_hit Counts number of loads that hit the L2 cache
82 0x02 ld_miss Counts the number of loads that miss the L2 cache
83 0x03 loads Counts all L2 load requests
84 0x04 rfo_hit Counts the number of store RFO requests that hit the L2 cache
85 0x08 rfo_miss Counts the number of store RFO requests that miss the L2 cache
86 0x0C rfos Counts all L2 store RFO requests
87 0x10 ifetch_hit Counts number of instruction fetches that hit the L2 cach
[all...]
/external/oprofile/events/i386/atom/
H A Devents23 event:0x21 counters:0,1 um:core minimum:6000 name:CORE : Cycles L2 address bus is in use
24 event:0x22 counters:0,1 um:core minimum:6000 name:L2_DBUS_BUSY : Cycles the L2 cache data bus is busy
25 event:0x24 counters:0,1 um:core,prefetch minimum:500 name:L2_LINES_IN : L2 cache misses
26 event:0x25 counters:0,1 um:core minimum:500 name:L2_M_LINES_IN : L2 cache line modifications
27 event:0x26 counters:0,1 um:core,prefetch minimum:500 name:L2_LINES_OUT : L2 cache lines evicted
28 event:0x27 counters:0,1 um:core,prefetch minimum:500 name:L2_M_LINES_OUT : Modified lines evicted from the L2 cache
29 event:0x28 counters:0,1 um:core,mesi minimum:6000 name:L2_IFETCH : L2 cacheable instruction fetch requests
30 event:0x29 counters:0,1 um:core,prefetch,mesi minimum:6000 name:L2_LD : L2 cache reads
31 event:0x2A counters:0,1 um:core,mesi minimum:6000 name:L2_ST : L2 store requests
32 event:0x2B counters:0,1 um:core,mesi minimum:6000 name:L2_LOCK : L2 locke
[all...]
/external/clang/test/FixIt/
H A Dfixit.c71 /*preserved comment*/ L2 : c++; // expected-warning {{unused label}}
/external/stlport/src/
H A Dlock_free_slist.h241 je L2 // Yes, we're done
246 L2:
268 je L2 // Yes, we're done
273 L2:
/external/openssl/crypto/des/times/
H A Daix.cc7 L2 Cache : 256 K
/external/llvm/include/llvm/ADT/
H A Dilist.h472 void transfer(iterator position, iplist &L2, iterator first, iterator last) { argument
480 NodeTy *L2Sentinel = L2.getTail();
481 L2.setTail(0);
489 L2.Head = Next;
507 this->transferNodesFromList(L2, First, PosNext);
510 L2.setTail(L2Sentinel);
552 void splice(iterator where, iplist &L2) { argument
553 if (!L2.empty())
554 transfer(where, L2, L2
556 splice(iterator where, iplist &L2, iterator first) argument
561 splice(iterator where, iplist &L2, iterator first, iterator last) argument
[all...]
H A DEquivalenceClasses.h217 member_iterator unionSets(member_iterator L1, member_iterator L2) { argument
218 assert(L1 != member_end() && L2 != member_end() && "Illegal inputs!");
219 if (L1 == L2) return L1; // Unifying the same two sets, noop.
222 // point to the L2 leader node.
223 const ECValue &L1LV = *L1.Node, &L2LV = *L2.Node;
229 // Clear L2's leader flag:
232 // L2's leader is now L1.
/external/libffi/src/frv/
H A Deabi.S109 bne icc0, 0, .L2
114 .L2:
/external/llvm/lib/VMCore/
H A DSymbolTableListTraitsImpl.h87 ::transferNodesFromList(ilist_traits<ValueSubClass> &L2, argument
91 ItemParentClass *NewIP = getListOwner(), *OldIP = L2.getListOwner();
/external/qemu/distrib/sdl-1.2.15/src/hermes/
H A Dmmxp2_32.asm73 jmp .L2
106 .L2:
137 jmp .L2 ; not necessary at the moment, but doesn't hurt (much)
170 .L2:
204 jmp .L2
241 .L2:
288 jmp near .L2
363 jz .L2
367 .L2:
/external/llvm/include/llvm/
H A DSymbolTableListTraits.h66 void transferNodesFromList(ilist_traits<ValueSubClass> &L2,

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