/external/llvm/lib/Target/CellSPU/ |
H A D | SPUInstrBuilder.h | 33 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0, argument 36 return MIB.addImm(Offset).addFrameIndex(FI); 38 return MIB.addFrameIndex(FI).addImm(Offset);
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H A D | SPUInstrInfo.cpp | 356 MachineInstrBuilder MIB; local 364 MIB = BuildMI(&MBB, DL, get(SPU::HBR_LABEL)).addSym(branchLabel); 370 MIB = BuildMI(&MBB, DL, get(SPU::BR)); 371 MIB.addMBB(TBB); 374 DEBUG((*MIB).dump()); 378 MIB = BuildMI( MBB, findHBRPosition(MBB), DL, get(SPU::HBRA)); 379 MIB.addSym(branchLabel); 380 MIB.addMBB(TBB); 384 MIB = BuildMI(&MBB, DL, get(Cond[0].getImm())); 385 MIB [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrBuilder.h | 33 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0, argument 36 return MIB.addImm(Offset).addFrameIndex(FI); 38 return MIB.addFrameIndex(FI).addImm(Offset);
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/external/llvm/lib/Target/X86/ |
H A D | X86InstrBuilder.h | 90 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) { argument 93 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0); 98 addOffset(const MachineInstrBuilder &MIB, int Offset) { argument 99 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0); 107 addRegOffset(const MachineInstrBuilder &MIB, argument 109 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); 114 static inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB, argument 117 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) 122 addFullAddress(const MachineInstrBuilder &MIB, argument 127 MIB 148 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0) argument 174 addConstantPoolReference(const MachineInstrBuilder &MIB, unsigned CPI, unsigned GlobalBaseReg, unsigned char OpFlags) argument [all...] |
H A D | X86InstrInfo.cpp | 1762 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(), local 1768 MIB.addReg(0).addImm(1 << ShAmt) 1774 addRegOffset(MIB, leaInReg, true, 1); 1778 addRegOffset(MIB, leaInReg, true, -1); 1784 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm()); 1795 addRegReg(MIB, leaInReg, true, leaInReg, false); 1800 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2); 1802 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY)) 1805 addRegReg(MIB, leaInReg, true, leaInReg2, true); 1813 MachineInstr *NewMI = MIB; 2964 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)); local 2998 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); local 3514 MachineInstrBuilder MIB = BuildMI(MF, DL, get(X86::DBG_VALUE)); local 3574 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode)); local [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMExpandPseudoInsts.cpp | 383 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), local 391 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); 393 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 395 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); 397 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); 400 MIB.addOperand(MI.getOperand(OpIdx++)); 403 MIB.addOperand(MI.getOperand(OpIdx++)); 404 MIB.addOperand(MI.getOperand(OpIdx++)); 407 MIB.addOperand(MI.getOperand(OpIdx++)); 417 MIB 448 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), local 500 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), local 584 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)); local 841 MachineInstrBuilder MIB = local 853 MachineInstrBuilder MIB = local 945 MachineInstrBuilder MIB = local 976 MachineInstrBuilder MIB = local 1008 MachineInstrBuilder MIB = local 1236 MachineInstrBuilder MIB = local [all...] |
H A D | Thumb1FrameLowering.cpp | 280 MachineInstrBuilder MIB = local 283 AddDefaultPred(MIB); 284 MIB->copyImplicitOps(&*MBBI); 304 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH)); local 305 AddDefaultPred(MIB); 323 MIB.addReg(Reg, getKillRegState(isKill)); 325 MIB.setMIFlags(MachineInstr::FrameSetup); 343 MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP)); local 344 AddDefaultPred(MIB); 354 (*MIB) [all...] |
H A D | Thumb1RegisterInfo.cpp | 130 MachineInstrBuilder MIB = local 133 MIB = AddDefaultT1CC(MIB); 135 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill); 137 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill); 138 AddDefaultPred(MIB); 242 const MachineInstrBuilder MIB = 245 AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal)); 261 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); local 263 MIB 269 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); local [all...] |
H A D | Thumb2SizeReduction.cpp | 456 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, TII->get(Opc)); local 458 MIB.addOperand(MI->getOperand(0)); 459 MIB.addOperand(MI->getOperand(1)); 462 MIB.addImm(OffsetImm / Scale); 467 MIB.addReg(OffsetReg, getKillRegState(OffsetKill)); 472 MIB.addOperand(MI->getOperand(OpNum)); 475 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); 478 MIB.setMIFlags(MI->getFlags()); 480 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB); local 517 MachineInstrBuilder MIB 527 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " <<*MIB); local 674 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID); local 696 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB); local 765 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID); local 803 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB); local [all...] |
H A D | ARMBaseInstrInfo.h | 314 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) { argument 315 return MIB.addImm((int64_t)ARMCC::AL).addReg(0); 319 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) { argument 320 return MIB.addReg(0); 324 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB, argument 326 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead)); 330 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) { argument 331 return MIB.addReg(0);
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H A D | ARMBaseInstrInfo.cpp | 675 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); local 676 MIB.addReg(SrcReg, getKillRegState(KillSrc)); 678 MIB.addReg(SrcReg, getKillRegState(KillSrc)); 679 AddDefaultPred(MIB); 743 MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, argument 747 return MIB.addReg(Reg, State); 750 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State); 751 return MIB.addReg(Reg, State, SubIdx); 818 MachineInstrBuilder MIB = local 822 MIB 839 MachineInstrBuilder MIB = local 853 MachineInstrBuilder MIB = local 985 MachineInstrBuilder MIB = local 1005 MachineInstrBuilder MIB = local 1021 MachineInstrBuilder MIB = local 1169 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE)) local 1237 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode), local [all...] |
H A D | MLxExpansionPass.cpp | 227 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg) local 231 MIB.addImm(LaneImm); 232 MIB.addImm(Pred).addReg(PredReg); 234 MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID2) 239 MIB.addReg(TmpReg, getKillRegState(true)) 242 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true)); 244 MIB.addImm(Pred).addReg(PredReg);
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H A D | ARMFastISel.cpp | 221 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB); 223 const MachineInstrBuilder &MIB, 269 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) { argument 270 MachineInstr *MI = &*MIB; 276 AddDefaultPred(MIB); 283 AddDefaultT1CC(MIB); 285 AddDefaultCC(MIB); 287 return MIB; 661 MachineInstrBuilder MIB; local 664 MIB 681 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, local 692 MachineInstrBuilder MIB; local 947 AddLoadStoreOperands(EVT VT, Address &Addr, const MachineInstrBuilder &MIB, unsigned Flags, bool useAM3) argument 1077 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, local 1191 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, local 1474 MachineInstrBuilder MIB; local 2223 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, local 2361 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, local 2583 MachineInstrBuilder MIB; local [all...] |
H A D | ARMFrameLowering.cpp | 222 MachineInstrBuilder MIB = local 226 AddDefaultCC(AddDefaultPred(MIB)); 445 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode)); local 447 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(), 451 MIB.addExternalSymbol(JumpTarget.getSymbolName(), 456 if (STI.isThumb()) MIB.addImm(ARMCC::AL).addReg(0); 626 MachineInstrBuilder MIB = local 630 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second)); 632 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc), local 637 AddDefaultPred(MIB); 691 MachineInstrBuilder MIB = local 706 MachineInstrBuilder MIB = local 789 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP) local [all...] |
H A D | Thumb2ITBlockPass.cpp | 181 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT)) local 189 MachineBasicBlock::iterator InsertPos = MIB; 232 MIB.addImm(Mask);
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H A D | ARMLoadStoreOptimizer.cpp | 349 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(Opcode)) 353 MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef) 358 MIB.addReg(ImpDefs[i], RegState::ImplicitDefine); 777 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(NewOpc)) local 784 MIB.addOperand(MI->getOperand(OpNum)); 787 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); 1082 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MBBI->getDebugLoc(), local 1086 MIB.addImm(Offset).addImm(Pred).addReg(PredReg); 1088 MachineInstrBuilder MIB local 1744 MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, MCID) local 1758 MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, MCID) local [all...] |
H A D | Thumb2InstrInfo.cpp | 279 MachineInstrBuilder MIB = 284 AddDefaultCC(MIB); 411 MachineInstrBuilder MIB(&MI); 412 AddDefaultPred(MIB);
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/external/llvm/lib/Target/Mips/ |
H A D | Mips16InstrInfo.cpp | 70 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); local 73 MIB.addReg(DestReg, RegState::Define); 76 MIB.addReg(ZeroReg); 79 MIB.addReg(SrcReg, getKillRegState(KillSrc));
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H A D | MipsInstrInfo.cpp | 68 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Mips::DBG_VALUE)) local 70 return &*MIB; 178 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID); local 181 MIB.addReg(Cond[i].getReg()); 183 MIB.addMBB(TBB);
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H A D | MipsSEInstrInfo.cpp | 142 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); local 145 MIB.addReg(DestReg, RegState::Define); 148 MIB.addReg(ZeroReg); 151 MIB.addReg(SrcReg, getKillRegState(KillSrc));
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/external/llvm/lib/CodeGen/ |
H A D | MachineInstrBundle.cpp | 109 MachineInstrBuilder MIB = BuildMI(MBB, FirstMI, FirstMI->getDebugLoc(), local 190 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) | 199 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) |
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H A D | MachineSSAUpdater.cpp | 190 MachineInstrBuilder MIB(InsertedPHI); 192 MIB.addReg(PredValues[i].second).addMBB(PredValues[i].first);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 652 MachineInstrBuilder MIB = BuildMI(*MF, DL, II); 663 MIB.addReg(0U); // undef 665 AddOperand(&*MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap, 671 MIB.addCImm(CI); 673 MIB.addImm(CI->getSExtValue()); 675 MIB.addFPImm(CF); 679 MIB.addReg(0U); 683 MIB.addReg(0U); 686 MIB [all...] |
/external/llvm/lib/Target/MBlaze/ |
H A D | MBlazeFrameLowering.cpp | 59 MachineInstr::mop_iterator MIB = MBB->operands_begin(); local 62 for (MachineInstr::mop_iterator MII = MIB; MII != MIE; ++MII) { 99 MachineBasicBlock::iterator MIB = MBB->begin(); local 121 for (MachineBasicBlock::iterator I=MIB; I != MIE; ++I) { 171 for (MachineBasicBlock::iterator I=MIB; I != MIE; ++I) {
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreInstrInfo.cpp | 393 MachineInstrBuilder MIB = BuildMI(MF, DL, get(XCore::DBG_VALUE)) local 395 return &*MIB;
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