Searched refs:PrintReg (Results 1 - 25 of 25) sorted by relevance

/external/llvm/lib/CodeGen/
H A DLiveRegMatrix.cpp73 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI)
74 << " to " << PrintReg(PhysReg, TRI) << ':');
88 DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI)
89 << " from " << PrintReg(PhysReg, TRI) << ':');
H A DRegAllocFast.cpp269 DEBUG(dbgs() << "Spilling " << PrintReg(LRI->VirtReg, TRI)
270 << " in " << PrintReg(LR.PhysReg, TRI));
433 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is already used in instr.\n");
442 DEBUG(dbgs() << PrintReg(VirtReg, TRI) << " corresponding "
443 << PrintReg(PhysReg, TRI) << " is reserved already.\n");
453 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is disabled.\n");
484 DEBUG(dbgs() << "Assigning " << PrintReg(LR.VirtReg, TRI) << " to "
485 << PrintReg(PhysReg, TRI) << "\n");
539 DEBUG(dbgs() << "Allocating " << PrintReg(VirtReg) << " from "
545 DEBUG(dbgs() << "\tRegister: " << PrintReg(*
[all...]
H A DVirtRegMap.cpp113 OS << '[' << PrintReg(Reg, TRI) << " -> "
114 << PrintReg(Virt2PhysMap[Reg], TRI) << "] "
122 OS << '[' << PrintReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg]
H A DRegAllocBase.cpp102 << ':' << PrintReg(VirtReg->reg) << ' ' << *VirtReg << '\n');
H A DRegisterClassInfo.cpp117 dbgs() << ' ' << PrintReg(RCI.Order[I], TRI);
H A DInlineSpiller.cpp315 OS << "spill " << PrintReg(SVI.SpillReg) << ':'
480 DEBUG(dbgs() << "Cached value " << PrintReg(UseReg) << ':'
485 DEBUG(dbgs() << "Tracing value " << PrintReg(UseReg) << ':'
497 DEBUG(dbgs() << " " << PrintReg(Reg) << ':' << VNI->id << '@' << VNI->def
584 DEBUG(dbgs() << "copy of " << PrintReg(SrcReg) << ':'
657 DEBUG(dbgs() << "Value " << PrintReg(Reg) << ':' << VNI->id << '@'
682 DEBUG(dbgs() << "Stale interval: " << PrintReg(SVI.SpillReg) << '\n');
689 DEBUG(dbgs() << "Stale value: " << PrintReg(SVI.SpillReg) << '\n');
1110 DEBUG(dbgs() << "spillAroundUses " << PrintReg(Reg) << '\n');
1280 << ':' << PrintReg(edi
[all...]
H A DRegisterCoalescer.cpp449 DEBUG(dbgs() << "Extending: " << PrintReg(IntB.reg, TRI));
961 DEBUG(dbgs() << "\tConsidering merging " << PrintReg(CP.getSrcReg(), TRI)
962 << " with " << PrintReg(CP.getDstReg(), TRI, CP.getSrcIdx())
978 dbgs() << PrintReg(CP.getDstReg()) << " in "
980 << PrintReg(CP.getSrcReg()) << " in "
983 dbgs() << PrintReg(CP.getSrcReg(), TRI) << " in "
984 << PrintReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n';
1055 dbgs() << "\tJoined. Result = " << PrintReg(CP.getDstReg(), TRI);
1070 DEBUG(dbgs() << "\t\tRHS = " << PrintReg(CP.getSrcReg()) << ' ' << RHS
1233 DEBUG(dbgs() << "\t\tRHS = " << PrintReg(C
[all...]
H A DRegAllocGreedy.cpp455 DEBUG(dbgs() << "missed hint " << PrintReg(Hint, TRI) << '\n');
470 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is available at cost " << Cost
595 DEBUG(dbgs() << "evicting " << PrintReg(PhysReg, TRI)
653 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " would clobber CSR "
654 << PrintReg(CSR, TRI) << '\n');
1147 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tno positive bundles\n");
1150 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tstatic = " << Cost);
1157 << PrintReg(GlobalCand[BestCand].PhysReg, TRI) << '\n';
1203 DEBUG(dbgs() << "Split for " << PrintReg(Cand.PhysReg, TRI) << " in "
1528 DEBUG(dbgs() << PrintReg(PhysRe
[all...]
H A DMachineFunction.cpp323 OS << PrintReg(I->first, TRI);
325 OS << " in " << PrintReg(I->second, TRI);
335 OS << ' ' << PrintReg(*I, TRI);
H A DRegAllocPBQP.cpp488 DEBUG(dbgs() << "VREG " << PrintReg(vreg, tri) << " -> "
498 DEBUG(dbgs() << "VREG " << PrintReg(vreg, tri) << " -> SPILLED (Cost: "
506 DEBUG(dbgs() << PrintReg((*itr)->reg, tri) << " ");
H A DPHIElimination.cpp236 DEBUG(dbgs() << "Reusing " << PrintReg(IncomingReg) << " for " << *MPhi);
456 DEBUG(dbgs() << PrintReg(Reg) << " live-out before critical edge BB#"
H A DLiveIntervalUnion.cpp90 << PrintReg(SI.value()->reg, TRI);
H A DMachineVerifier.cpp401 *OS << PrintReg(LI.reg, TRI);
412 *OS << PrintReg(LI.reg, TRI);
1247 *OS << "Virtual register " << PrintReg(*I)
1280 *OS << "Virtual register " << PrintReg(Reg)
1286 *OS << "Virtual register " << PrintReg(Reg)
1305 *OS << PrintReg(Reg, TRI) << " still has defs or uses\n";
H A DLiveRangeEdit.cpp376 DEBUG(dbgs() << "Inflated " << PrintReg(LI.reg) << " to "
H A DRegisterPressure.cpp70 dbgs() << PrintReg(LiveInRegs[i], TRI) << " ";
74 dbgs() << PrintReg(LiveOutRegs[i], TRI) << " ";
H A DMachineInstr.cpp267 OS << PrintReg(getReg(), TRI, getSubReg());
1707 OS << " " << RC->getName() << ':' << PrintReg(VirtRegs[i]);
1714 OS << "," << PrintReg(VirtRegs[j]);
H A DScheduleDAG.cpp316 dbgs() << " Reg=" << PrintReg(I->getReg(), G->TRI);
H A DLiveIntervalAnalysis.cpp148 OS << PrintReg(Reg) << " = " << getInterval(Reg) << '\n';
206 DEBUG(dbgs() << "\t\tregister: " << PrintReg(interval.reg, TRI));
H A DMachineBasicBlock.cpp288 OS << ' ' << PrintReg(*I, TRI);
H A DMachineTraceMetrics.cpp1008 DEBUG(dbgs() << ' ' << PrintReg(LIR.Reg) << '@' << LIR.Height);
/external/llvm/include/llvm/Target/
H A DTargetRegisterInfo.h834 /// PrintReg - Helper class for printing registers on a raw_ostream.
844 /// Usage: OS << PrintReg(Reg, TRI) << '\n';
846 class PrintReg { class in namespace:llvm
851 PrintReg(unsigned reg, const TargetRegisterInfo *tri = 0, unsigned subidx = 0) function in class:llvm::PrintReg
856 static inline raw_ostream &operator<<(raw_ostream &OS, const PrintReg &PR) {
/external/llvm/lib/Target/
H A DTargetRegisterInfo.cpp30 void PrintReg::print(raw_ostream &OS) const {
/external/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp426 OS << ' ' << PrintReg(R->getReg(), G ? G->getTarget().getRegisterInfo() :0);
/external/llvm/lib/Target/Hexagon/
H A DHexagonHardwareLoops.cpp158 if (isReg()) { OS << PrintReg(getReg()); }
/external/llvm/lib/Target/PowerPC/
H A DPPCCTRLoops.cpp171 if (isReg()) { OS << PrintReg(getReg()); }

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