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Searched refs:Rn (Results 1 - 8 of 8) sorted by relevance

/external/llvm/lib/Target/ARM/Disassembler/
H A D	ARMDisassembler.cpp	1227 // Writeback not allowed if Rn is in the target list. 1301 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 1346 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1442 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 1461 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1481 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1488 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1502 if (writeback && (Rn == 15 \|\| Rn == Rt)) 1545 unsigned Rn local 1587 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 1777 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 1807 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 2022 unsigned Rn = fieldFromInstruction(Insn, 0, 4); local 2051 unsigned Rn = fieldFromInstruction(Val, 13, 4); local 2069 unsigned Rn = fieldFromInstruction(Val, 9, 4); local 2155 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 2429 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 2699 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 2746 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 2794 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 2829 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 2972 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 3054 unsigned Rn = fieldFromInstruction(Val, 0, 3); local 3069 unsigned Rn = fieldFromInstruction(Val, 0, 3); local 3101 unsigned Rn = fieldFromInstruction(Val, 6, 4); local 3130 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 3187 unsigned Rn = fieldFromInstruction(Val, 9, 4); local 3202 unsigned Rn = fieldFromInstruction(Val, 8, 4); local 3230 unsigned Rn = fieldFromInstruction(Val, 9, 4); local 3262 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 3291 unsigned Rn = fieldFromInstruction(Val, 13, 4); local 3400 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 3538 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 3562 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 3587 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 3612 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 3640 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 3665 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 3690 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 3757 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 3823 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 3890 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 3954 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 4024 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 4088 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 4169 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 4317 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 4354 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 4412 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 4495 unsigned Rn = fieldFromInstruction(Val, 16, 4); local [all...]
/external/qemu/
H A D	trace.c	896 int Rn = (insn >> 12) & 15; local 899 result += _interlock_use(Rn); 901 if (Rn != 0) /* UNDEFINED */ 934 int Rn = (insn >> 16) & 15; local 936 result += _interlock_use(Rn) + _interlock_use(Rm); 943 int Rn = (insn >> 16) & 15; local 945 result += _interlock_use(Rn); 957 int Rn = (insn >> 16) & 15; local 959 result += _interlock_use(Rn) + _interlock_use(Rm); 970 int Rn local 1018 int Rn = (insn >> 16) & 15; local 1035 int Rn = (insn >> 12) & 15; local 1042 int Rn = (insn >> 16) & 15; local 1060 int Rn = (insn >> 16) & 15; local 1077 int Rn = (insn >> 16) & 15; local 1110 int Rn = (insn >> 16) & 15; local 1199 int Rn = (insn >> 3) & 7; local 1239 int Rn = (insn & 7) \| ((insn >> 4) & 0x8); local 1270 int Rn = (insn >> 3) & 7; local 1300 int Rn = (insn >> 3) & 7; local 1309 int Rn = (insn >> 3) & 7; local 1319 int Rn = (insn >> 3) & 7; local 1329 int Rn = (insn >> 3) & 7; local 1338 int Rn = (insn >> 3) & 7; local [all...]
H A D	arm-dis.c	`3450 unsigned int Rn = (given & 0x000f0000) >> 16; local 3458 func (stream, "[%s", arm_regnames[Rn]); 3461 else if (Rn == 15) /* 12-bit negative immediate offset */ 3517 if (Rn == 15) 3531 unsigned int Rn = (given & 0x000f0000) >> 16; local 3534 func (stream, "[%s", arm_regnames[Rn]);`
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A D	ARMMCCodeEmitter.cpp	709 // [Rn, Rm] 711 // {2-0} = Rn 714 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO1.getReg()); local 716 return (Rm << 3) \| Rn; 731 Reg = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC. 811 Reg = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC. 930 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO.getReg()); local 937 // {16-13} = Rn 945 Binary \|= Rn << 13; 956 // {17-14} Rn 961 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO.getReg()); local 1033 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC. local 1043 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO.getReg()); local 1078 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO.getReg()); local [all...]
/external/v8/src/arm/
H A D	disasm-arm.cc	`324 if (format[1] == 'n') { // 'rn: Rn register 692 // Rn field to encode it. 696 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the 697 // Rn field to encode the Rd register and the Rd field to encode 698 // the Rn register. 703 // when referring to the target registers. They are mapped to the Rn 706 // RdHi == Rn field`
/external/valgrind/main/none/tests/arm/
H A D	vfp.stdout.exp	871 vldr d9, [r6, #+4] :: Dd 0x0000011a 0x00000dd3 (int) (Rn + shift) 0x0dd3 872 vldr d16, [r9, #-4] :: Dd 0x00000cc2 0x00000bb1 (int) (Rn + shift) 0x0bb1 873 vldr d30, [r12] :: Dd 0x00000dd3 0x00000cc2 (int) (Rn + shift) 0x0cc2 874 vldr d22, [r9, #+8] :: Dd 0x0000022b 0x0000011a (int) (Rn + shift) 0x011a 875 vldr d29, [r2, #-8] :: Dd 0x00000bb1 0x00000aa0 (int) (Rn + shift) 0x0aa0 876 vldr d8, [r8, #+8] :: Dd 0x0000022b 0x0000011a (int) (Rn + shift) 0x011a 877 vldr d11, [r12, #-4] :: Dd 0x00000cc2 0x00000bb1 (int) (Rn + shift) 0x0bb1 878 vldr d18, [r3] :: Dd 0x00000dd3 0x00000cc2 (int) (Rn + shift) 0x0cc2 879 vldr d5, [r10, #+8] :: Dd 0x0000022b 0x0000011a (int) (Rn + shift) 0x011a 880 vldr d17, [r10] :: Dd 0x00000dd3 0x00000cc2 (int) (Rn [all...]
H A D	v6intThumb.stdout.exp	`558 ADDS-16 Rd, Rn, #imm3 567 ADDS-16 Rd, Rn, Rm 620 SUBS-16 Rd, Rn, Rm 673 ADDS-16 Rn, #uimm8 690 SUBS-16 Rn, #uimm8 707 CMP-16 Rn, #uimm8 736 MOVS-16 Rn, #uimm8 832 (T3) ADD{S}.W Rd, Rn, #constT [allegedly] 937 (T4) ADDW Rd, Rn, #uimm12 962 (T3) CMP.W Rn, #const [all...]`
/external/llvm/lib/Target/ARM/AsmParser/
H A D	ARMAsmParser.cpp	4140 // If we have a three-operand form, make sure to set Rn to be the operand 5320 unsigned Rn = Inst.getOperand(0).getReg(); local 5325 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo()) 5694 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5716 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5740 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5766 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5792 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5814 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5838 TmpInst.addOperand(Inst.getOperand(2)); // Rn 7119 unsigned Rn = Inst.getOperand(0).getReg(); local 7143 unsigned Rn = Inst.getOperand(0).getReg(); local [all...]

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