/external/llvm/lib/Target/ARM/ |
H A D | ARMSelectionDAGInfo.h | 26 case ISD::SHL: return ARM_AM::lsl;
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/external/dexmaker/src/dx/java/com/android/dx/rop/code/ |
H A D | RegOps.java | 115 public static final int SHL = 23; field in class:RegOps 336 case SHL: return "shl";
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H A D | DexTranslationAdvice.java | 88 case RegOps.SHL:
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H A D | Rops.java | 339 new Rop(RegOps.SHL, Type.INT, StdTypeList.INT_INT, "shl-int"); 343 new Rop(RegOps.SHL, Type.LONG, StdTypeList.LONG_INT, "shl-long"); 484 new Rop(RegOps.SHL, Type.INT, StdTypeList.INT, "shl-const-int"); 488 new Rop(RegOps.SHL, Type.LONG, StdTypeList.INT, "shl-const-long"); 1147 case RegOps.SHL: return opShl(sources);
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/external/libvpx/build/make/ |
H A D | ads2gas.pl | 41 # Convert :SHL: to << 42 s/:SHL:/ << /g;
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H A D | ads2gas_apple.pl | 59 # Convert :SHL: to << 60 s/:SHL:/ << /g;
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/external/v8/src/ |
H A D | token.h | 99 T(SHL, "<<", 11) \ 269 return (SHL <= op) && (op <= SHR);
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H A D | builtins.h | 240 V(SHL, 1) \
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H A D | runtime.js | 304 function SHL(y) { function
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 362 if (Opcode == ISD::SHL) { 413 if (Op0.getOperand(0).getOpcode() == ISD::SHL || 415 if (Op1.getOperand(0).getOpcode() != ISD::SHL && 422 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) { 423 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL && 435 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) && 438 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value; 442 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && 445 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value; 1035 case ISD::SHL [all...] |
H A D | PPCISelLowering.h | 91 SRL, SRA, SHL, enumerator in enum:llvm::PPCISD::NodeType
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/external/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 316 SHL, SRA, SRL, ROTL, ROTR, enumerator in enum:llvm::ISD::NodeType 380 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
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/external/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.h | 64 /// SHL, SRA, SRL - Non-constant shifts. 65 SHL, SRA, SRL enumerator in enum:llvm::MSP430ISD::__anon8933
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H A D | MSP430ISelLowering.cpp | 96 setOperationAction(ISD::SHL, MVT::i8, Custom); 99 setOperationAction(ISD::SHL, MVT::i16, Custom); 183 case ISD::SHL: // FALLTHROUGH 601 case ISD::SHL: 602 return DAG.getNode(MSP430ISD::SHL, dl, 627 Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA), 983 case MSP430ISD::SHL: return "MSP430ISD::SHL";
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeIntegerTypes.cpp | 71 case ISD::SHL: Res = PromoteIntRes_SHL(N); break; 534 return DAG.getNode(ISD::SHL, N->getDebugLoc(), 719 Part = DAG.getNode(ISD::SHL, dl, NVT, Part, 786 case ISD::SHL: 891 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi, 1152 case ISD::SHL: 1269 if (N->getOpcode() == ISD::SHL) { 1274 Hi = DAG.getNode(ISD::SHL, DL, 1289 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, ShTy)); 1291 DAG.getNode(ISD::SHL, D [all...] |
H A D | DAGCombiner.cpp | 1112 case ISD::SHL: return visitSHL(N); 1195 case ISD::SHL: 1355 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 1357 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 1474 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1478 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1484 if (N1.getOpcode() == ISD::SHL && 1490 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1493 if (N0.getOpcode() == ISD::SHL && 1499 DAG.getNode(ISD::SHL, [all...] |
H A D | LegalizeDAG.cpp | 554 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); 1000 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1030 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1257 case ISD::SHL: 1523 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit, 2327 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2331 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2332 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2341 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2342 Tmp7 = DAG.getNode(ISD::SHL, d [all...] |
H A D | TargetLowering.cpp | 1417 case ISD::SHL: 1433 unsigned Opc = ISD::SHL; 1459 isTypeDesirableForOp(ISD::SHL, InnerVT)) { 1464 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp, 1493 if (InOp.getOpcode() == ISD::SHL && 1501 Opc = ISD::SHL; 1586 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, 1792 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 1793 // place. We expect the SHL to be eliminated by other optimizations. 1800 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, d [all...] |
/external/speex/libspeex/ |
H A D | arch.h | 178 #define SHL(a,shift) (a) macro
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H A D | fixed_generic.h | 60 #define SHL(a,shift) ((spx_word32_t)(a) << (shift)) macro
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/external/dexmaker/src/dx/java/com/android/dx/ssa/ |
H A D | SCCP.java | 437 case RegOps.SHL: 516 case RegOps.SHL:
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/external/openssl/crypto/sha/asm/ |
H A D | sha512-ppc.pl | 46 $SHL="sldi"; 54 $SHL="slwi"; 187 $SHL $num,$num,`log(16*$SZ)/log(2)`
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/external/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 715 if (Shl.getOpcode() != ISD::SHL) 1844 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 1847 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31); 1891 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1); 1901 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY, 1932 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 1957 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1); 2041 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt); 2043 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt); 2075 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, D [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 753 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand); 989 setOperationAction(ISD::SHL, MVT::v8i16, Custom); 990 setOperationAction(ISD::SHL, MVT::v16i8, Custom); 999 setOperationAction(ISD::SHL, MVT::v2i64, Legal); 1000 setOperationAction(ISD::SHL, MVT::v4i32, Legal); 1007 setOperationAction(ISD::SHL, MVT::v2i64, Custom); 1008 setOperationAction(ISD::SHL, MVT::v4i32, Custom); 1053 setOperationAction(ISD::SHL, MVT::v16i16, Custom); 1054 setOperationAction(ISD::SHL, MVT::v32i8, Custom); 1103 setOperationAction(ISD::SHL, MV 10720 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R, local 10764 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R, local [all...] |
/external/v8/src/ia32/ |
H A D | code-stubs-ia32.cc | 1261 case Token::SHL: 1299 case Token::SHL: 1430 case Token::SHL: 1445 case Token::SHL: 1473 case Token::SHL: 1489 ASSERT_EQ(Token::SHL, op_); 1572 case Token::SHL: 1607 case Token::SHL: 1634 case Token::SHL: 1755 case Token::SHL [all...] |