Searched refs:SuperReg (Results 1 - 4 of 4) sorted by relevance
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonFrameLowering.cpp | 216 unsigned SuperReg = *SRI; local 219 return SuperReg; 248 unsigned SuperReg = uniqueSuperReg(Reg, TRI); local 254 SuperRegClass = TRI->getMinimalPhysRegClass(SuperReg); 255 CanUseDblStore = (SuperRegNext == SuperReg); 260 TII.storeRegToStackSlot(MBB, MI, SuperReg, true, 262 MBB.addLiveIn(SuperReg); 303 unsigned SuperReg = uniqueSuperReg(Reg, TRI); local 308 SuperRegClass = TRI->getMinimalPhysRegClass(SuperReg); 309 CanUseDblLoad = (SuperRegNext == SuperReg); [all...] |
/external/llvm/lib/CodeGen/ |
H A D | AggressiveAntiDepBreaker.cpp | 566 unsigned SuperReg = 0; 569 if ((SuperReg == 0) || TRI->isSuperRegister(SuperReg, Reg)) 570 SuperReg = Reg; 586 // All group registers should be a subreg of SuperReg. 589 if (Reg == SuperReg) continue; 590 bool IsSub = TRI->isSubRegister(SuperReg, Reg); 603 dbgs() << "*** Performing rename " << TRI->getName(SuperReg) << 608 // Check each possible rename register for SuperReg in round-robin 617 TRI->getMinimalPhysRegClass(SuperReg, MV [all...] |
H A D | PostRASchedulerList.cpp | 469 const unsigned SuperReg = MO.getReg(); local 470 for (MCSubRegIterator SubRegs(SuperReg, TRI); SubRegs.isValid(); ++SubRegs) {
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/external/llvm/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 1711 SDValue SuperReg = SDValue(VLd, 0); 1717 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); 1944 SDValue SuperReg; local 1949 SuperReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0); 1951 SuperReg = SDValue(PairQRegs(MVT::v4i64, V0, V1), 0); 1958 SuperReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0); 1960 SuperReg = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0); 1962 Ops.push_back(SuperReg); 1977 SuperReg = SDValue(VLdLn, 0); 1983 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); 2032 SDValue SuperReg; local [all...] |
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